Ex Parte Tischler

Board of Patent Appeals and Interferences

Mar 29, 2011

11222615 (B.P.A.I. Mar. 29, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte BRETT A. TISCHLER
____________

Appeal 2009-009680
Application 11/222,615
Technology Center 2100
____________

Before JOSEPH L. DIXON, HOWARD B. BLANKENSHIP, and
ST. JOHN COURTENAY, III, Administrative Patent Judges.

BLANKENSHIP, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1, 3, 4, 6-9, 11, 12, 15-17, 19, and 20, which are all the
claims remaining in the application. We have jurisdiction under 35 U.S.C. §
6(b).
We affirm.
Appeal 2009-009680
Application 11/222,615

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Invention
Appellant’s invention relates to processing memory access requests,
and in particular to dispatching a first memory access request to a memory
controller and dispatching a second memory access request to the controller
in response to an anticipated completion of a memory access operation
represented by the first memory access request. Abstract.

Representative Claim
1. A method comprising:

dispatching a first memory access request to a memory controller; and

dispatching a second memory access request to the memory controller at a
predetermined duration before an actual completion of a memory
access operation represented by the first memory access request.

Examiner’s Rejections
Claims 1, 6-9, 11, 12, 15, 16, 19, and 20 stand rejected under 35
U.S.C. § 103(a) as being unpatentable over Zagorianakos (US 2003/0185032
A1) and Chao (US 7,099,972 B2).
Claims 3, 4, and 17 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Zagorianakos, Chao, and Lai (US 2003/0070018 A1).

Claim Groupings
Based on Appellant’s arguments in the Appeal Brief, we will decide
the appeal on the basis of claim 1 and claim 9. See 37 C.F.R. §
41.37(c)(1)(vii).
Appeal 2009-009680
Application 11/222,615

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FINDINGS OF FACT
We rely on the Examiner’s findings set forth in the Answer.

ANALYSIS
Appellant argues that the combination of Zagorianakos and Chao fails
to teach dispatching a second memory access request to the memory
controller “at a predetermined duration before” an actual completion of a
memory access operation represented by the first memory access request.
The Examiner illustrates, at page 5 of the Answer, how Zagorianakos
(e.g., Fig. 3) teaches dispatching a second memory access request prior to
actual completion of a memory access operation represented by a first
memory access request. The Examiner finds that the different clock cycles
appear to represent a “predetermined duration” as claimed. Ans. 5.
Appellant filed a Reply Brief, but did not respond to the Examiner’s finding.
We agree with the Examiner to the extent that the system clock, as
shown in Figure 3 of Zagorianakos, predetermines the time duration between
the second memory access request (A2) and the actual completion of the
first memory access request (D1). Namely, A2 (at clock cycle 3) occurs at a
predetermined duration -- predetermined by the clock cycle time -- before
D1 (at clock cycle 7). There may be additional clock cycles between the
time of dispatching the second memory access request to the memory
controller, before the memory controller initiates the second memory access
at clock cycle 3 (see Zagorianakos ¶ [0023]), but that is also part of a
synchronous operation having a duration predetermined by the system clock.
Although the “predetermined duration” may not necessarily always be the
number of clock cycles shown in Figure 3, instant claim 1 does not
Appeal 2009-009680
Application 11/222,615

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distinguish over the “predetermined duration” being different between one
access and completion, and another access and completion. “What matters
is the objective reach of the claim. If the claim extends to what is obvious, it
is invalid under § 103.” KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 419
(2007).
We therefore find that Zagorianakos, taken alone, teaches all that is
required by instant claim 1. Appellant has not shown otherwise in the briefs.
We do not reach Appellant’s allegation of “lack of motivation” to combine
Zagorianakos and Chao.
In defense of claim 9, Appellant alleges that the references fail to
disclose or render obvious the feature that while a first memory access
request is received at a bus interface unit prior to a third memory access
request, the third memory access request is dispatched prior to the first
memory access request. App. Br. 12-13. However, the Examiner explains
how Zagorianakos is deemed to teach the argued feature (Ans. 7-8).
Although the Examiner’s findings in support of the rejection of claim 9 are
different from those set forth in the Final Rejection, Appellant had the right
to file a response telling us why the findings in the Answer should be
considered erroneous. Appellant did file the Reply Brief, but did not offer
any arguments in support of why any of the specific limitations of claim 9
should prevail if claim 1 were to fall. As we perceive no errors in the
Examiner’s findings in support of the rejection of claim 9 as set forth in the
Answer, we are not persuaded that claim 9 has been rejected in error.
We are therefore not persuaded that any claim on appeal has been
rejected in error. We sustain the Examiner’s rejections under 35 U.S.C. §
103(a).
Appeal 2009-009680
Application 11/222,615

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DECISION
The rejection of claims 1, 6-9, 11, 12, 15, 16, 19, and 20 under 35
U.S.C. § 103(a) as being unpatentable over Zagorianakos and Chao is
affirmed.
The rejection of claims 3, 4, and 17 under 35 U.S.C. § 103(a) as being
unpatentable over Zagorianakos, Chao, and Lai is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. §
41.50(f).

AFFIRMED

erc