Ex Parte Talbot et al

Board of Patent Appeals and Interferences

Dec 12, 2011

10842298 (B.P.A.I. Dec. 12, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte GERALD R. TALBOT, FREDERICK D. WEBER,
and SHWETAL A. PATEL
___________

Appeal 2009-014815
Application 10/842,298
Technology Center 2100
____________

Before ROBERT E. NAPPI, DAVID M. KOHUT, and
JASON V. MORGAN, Administrative Patent Judges.

MORGAN, Administrative Patent Judge.

DECISION ON APPEAL
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STATEMENT OF THE CASE
Introduction
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1, 4, 6 – 14, and 24 – 26. We have jurisdiction under 35 U.S.C.
§ 6(b). We affirm.
Exemplary Claim
1. A system comprising:
one or more processor nodes; and
a system memory connected to one of the one or more
processor nodes, wherein the system memory includes a
plurality of memory modules coupled serially in a chain to the
one of the one or more processor nodes and wherein one of said
plurality of memory modules includes a
plurality of memory chips mounted thereon,
wherein the one of said plurality of memory modules
further includes a memory module cache for storing data, stored
in said system memory including data stored in said system
memory that is not stored in the one of said plurality of memory
modules, and wherein the one of said plurality of memory
modules further includes a memory control hub including a
controller configured to determine whether data associated with
a received memory request is stored within either said memory
module cache or the plurality of memory chips mounted
thereon, said controller of said memory control hub configured
to access said memory module cache in response to determining
that said data associated with a received memory request is
stored within said memory module cache said controller of said
memory control hub further configured to access said plurality
of memory chips mounted on the one of said plurality of
memory modules in response to determining that said data
associated with a received memory request is stored within said
plurality of memory chips.

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Rejections on Appeal
The Examiner rejected claims 1, 4, 6 – 11, and 26 under 35 U.S.C.
§ 103(a) as unpatentable over Jeddeloh (US 2004/0024978 A1) in view of
Peters (US 6,249,840 B1) (Ans. 4 – 12).
The Examiner rejected claim 12 under 35 U.S.C. § 103(a) as
unpatentable over Jeddeloh in view of Peters in further view of Pritty (US
5,434,861) (Ans. 12 – 13).
The Examiner rejected claims 13 and 14 under 35 U.S.C. § 103(a) as
unpatentable over Jeddeloh in view of Peters in view of Pritty in further
view of Miller (US 6,553,446 B1) (Ans. 14 – 15).
The Examiner rejected claims 24 and 25 under 35 U.S.C. § 103(a) as
unpatentable over Jeddeloh in view of Peters in further view of Billard (US
5,983,323) (Ans. 16 – 18).
Issues on Appeal
Did the Examiner err in rejecting claim 1 under 35 U.S.C. § 103(a)
because the combination of Jeddeloh and Peters does not teach or suggest
that one of said plurality of memory modules further includes a memory
module cache for storing data stored in said system memory including data
stored in said system memory that is not stored in the one of said plurality of
memory modules?
Did the Examiner err in rejecting claim 1 under 35 U.S.C. § 103(a)
because Jeddeloh and Peters are non-analogous art and the Examiner
provided no motivation to combine the references?
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ANALYSIS
Claim 1 — memory module cache
Appellants contend that the combination of Jeddeloh and Peters does
not teach or suggest that one of said plurality of memory modules further
includes a memory module cache for storing data in said system memory
including data stored in said system memory that is not stored in the one of
said plurality of memory modules as recited in claim 1 (App. Br. 12). We
disagree.
Appellants admit that Jeddeloh in view of Peters teaches or suggests
“a system having a plurality of memory modules, each of the plurality of
memory modules including a plurality of memory chips mounted thereon,
where the memory chips may include a cache for storing information stored
in that memory chip or in other memory chips” (App. Br. 12). However,
Appellants argue that neither reference teaches or suggests a memory
module cache that stores data from the memory chips mounted on the
memory module and data from another memory module (App. Br. 12 – 13).
Appellants’ argument is based on the contention that Peters’ cache
register 68 is not the same as Appellants’ claimed memory module cache
(App. Br. 12). We disagree. The Examiner interprets the term “memory
module” as “any memory device that stores data, having any number of
chips” (Ans. 22). We agree with the Examiner as we find this interpretation
to be reasonable. Since Peters teaches that the “DRAM devices provide a
relatively inexpensive memory at which to store relatively large amounts of
data” (col. 1, ll. 53 – 54) (emphases added), we agree with the Examiner that
they are the same as the claimed “memory module.”
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The Examiner also finds that Peters teaches that its DRAM banks
each have a corresponding SRAM (Static Random Access Memory) cache
wherein each of the caches stores data of the corresponding DRAM bank or
any other DRAM bank (Ans. 6 – 7 and 21; Peters col. 4, ll. 53 – 58). As
such, we agree with the Examiner, that Peters teaches one of said plurality of
memory modules (a DRAM bank) further includes a memory module cache
(a SRAM cache) for storing data stored in said system memory including
data stored in said system memory that is not stored in the one of said
plurality of memory modules (where the SRAM caches data in other DRAM
banks).
Accordingly, we find no error with respect to this issue in the
Examiner’s rejection of claim 1.
Claim 1 — Jeddeloh and Peters
Appellants further contend that Jeddeloh and Peters are non-analogous
art (App. Br. 13). We do not find Appellants arguments persuasive.
Two criteria have evolved for determining whether prior art is
analogous: (1) whether the art is from the same field of endeavor,
regardless of the problem addressed, and (2) if the reference is not
within the field of the inventor's endeavor, whether the reference
still is reasonably pertinent to the particular problem with which
the inventor is involved.
In re Clay, 966 F.2d 656, 658-59 (Fed. Cir. 1992). See also In re Deminski,
796 F.2d 436, 442 (Fed. Cir. 1986); In re Wood, 599 F.2d 1032, 1036
(CCPA 1979).
We find that both Jeddeloh and Peters are from the same field of
endeavor: memory devices including access and control.
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Appellants further contend that there is no motivation to combine
Jeddeloh and Peters (App. Br. 13). We disagree. The Examiner has clearly
stated a motivation to combine the references:
It would have been obvious to one of ordinary skill
in the art to modify the system memory comprising
multiple memory modules, which comprise
multiple memory chips and a memory module
cache as taught by Jeddeloh and further have this
memory module cache store data in system
memory, including data stored in said system
memory that is not stored in the one of said
plurality of memory modules as taught by Peters,
since Peters discloses that having a memory
system wherein a memory module cache stores
data of the corresponding memory module, and
also of other memory modules provides the
advantages of [improving rates of data retrieval
operations (col. 2, lines 12-26)].
(Ans. 21).
We find the Examiner’s articulated reasoning with some rationale
underpinning for the combination of Jeddeloh and Peters to be reasonable.
Accordingly, we find no error with respect to this issue in the
Examiner’s rejection of claim 1.
Claims 4, 6 – 11, and 26
Appellants make the same arguments with respect to claims 4, 6 – 11,
and 26 as with claim 1 (App. Br. 16 – 17). Thus, for the same reasons
discussed supra, we find no error in the Examiner’s rejection of these
claims.
Claim 12
Appellants provide no additional arguments with respect to claim 12,
which is dependent on claim 1, except to argue that Pritty does not teach,
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disclose, or suggest the disputed recitation of claim 1 (App. Br. 17).
However, the Examiner does not rely on Pritty for the disputed recitation.
Thus, for the same reasons discussed supra, we find no error in the
Examiner’s rejection of this claim.
Claim 13
Appellants provide no additional arguments with respect to claim 13,
which is dependent on claim 1, except to argue that Miller does not teach,
disclose, or suggest the disputed recitation of claim 1 (App. Br. 18).
However, the Examiner does not rely on Miller for the disputed recitation.
Thus, for the same reasons discussed supra, we find no error in the
Examiner’s rejection of this claim.
Claim 14
Appellants provide no additional arguments with respect to claim 14,
which is dependent on claim 1, except to argue that the disputed recitation of
claim 1 would not have been obvious (App. Br. 18 – 19). Thus, for the same
reasons discussed supra, we find no error in the Examiner’s rejection of this
claim.
Claims 24 and 25
Appellants provide no additional arguments with respect to claims 24
and 25, which are dependent on claim 1, except to argue that Billard does
not teach, disclose, or suggest the disputed recitation of claim 1 (App. Br.
20). However, the Examiner does not rely on Billard for the disputed
recitation. Thus, for the same reasons discussed supra, we find no error in
the Examiner’s rejection of these claims.
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CONCLUSIONS
The Examiner has not erred in rejecting claims 1, 4, 6 – 14, and 24 –
26 under 35 U.S.C. § 103(a).
DECISION
The Examiner’s rejection of claims 1, 4, 6 – 14, and 24 – 26 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

ELD