Ex Parte Talbot

Patent Trial and Appeal Board

Sep 24, 2013

11590285 (P.T.A.B. Sep. 24, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte GERALD R. TALBOT1
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Appeal 2011-003796
Application 11/590,285
Technology Center 2100
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Before JOSEPH F. RUGGIERO, JASON V. MORGAN, and
LARRY J. HUME, Administrative Patent Judges.

MORGAN, Administrative Patent Judge.

DECISION ON APPEAL

1 Advanced Micro Devices, Inc., is the real party in interest. App. Br. 2.
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STATEMENT OF THE CASE
Introduction
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s Final
Rejection of claims 24–49. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Invention
Appellant invented a memory system that includes one or more
memory units, each including one or more memory devices and a parallel
interconnect. See Spec., Abstract.
Exemplary Claim (Emphases Added)
24. A memory system comprising:
one or more memory units each including one or more
memory devices and a parallel interconnect;
one or more buffer units coupled to the one or more
memory units via the parallel interconnect; and
a memory controller coupled to each of the one or more
buffer units via a respective serial interconnect, and coupled to
the one or more memory units via the parallel interconnect;
wherein each of the one or more memory units is
configured to receive a clock signal from the memory controller
via one or more clock signal paths of the parallel interconnect;
wherein each of the one or more buffer units is
configured to receive data from the memory controller via the
respective serial interconnect and to transmit the data to the one
or more memory units via the parallel interconnect, in response
to receiving command information from the memory controller;
and
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wherein the memory controller is configured to
asymmetrically control data transfer between the memory
controller and the one or more buffer units by adjusting a phase
of data transmitted by the memory controller based upon
information received from the one or more buffer units.
Rejections
The Examiner rejects claims 24–49 under a non-statutory
obviousness-type double patenting rejection as being unpatentable over
previously co-pending application number 11/590,290, which issued on
December 28, 2010, as patent number 7,861,140 (Talbot ’140).2
The Examiner rejects claims 24–31, 33, 34, and 36 under 35 U.S.C.
§ 103(a) as being unpatentable over Perego (U.S. 6,502,161 B1; Dec. 31,
2002) and Osaka (U.S. 2003/0200407 A1; Oct. 23, 2003). Ans. 7–12.
The Examiner rejects claims 32 and 35 under 35 U.S.C. § 103(a) as
being unpatentable over Perego, Osaka, and Vogt (U.S. 7,165,153 B2; Jan.
16, 2007; filed June 4, 2003). Ans. 13–14.
The Examiner rejects claims 37–44, 46, 47, and 49 under 35 U.S.C.
§ 103(a) as being unpatentable over Perego, Osaka, and Kim (U.S.
2007/0038831 A1; Feb. 15, 2007; filed May 2, 2006). Ans. 14–17.
The Examiner rejects claims 45 and 48 under 35 U.S.C. § 103(a) as
being unpatentable over Perego, Osaka, Kim, and Vogt. Ans. 17–18.

2 Because Talbot ’140 issued without change to the claims underlying the
Examiner’s rejection, this rejection is no longer provisional and we will refer
to the issued patent, rather than the underlying patent application, in the
Decision.
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ISSUES
1. Did the Examiner err in concluding that Talbot ’140 teaches or
suggests “a memory controller . . . coupled to the one or more memory units
via the parallel interconnect; wherein each of the one or more memory units
is configured to receive a clock signal from the memory controller via one or
more clock signal paths of the parallel interconnect,” as recited in claim 24?
2. Did the Examiner err in concluding that the combination of Perego
and Osaka teaches or suggests: (1) “wherein each of the one or more
memory units is configured to receive a clock signal from the memory
controller” and (2) “wherein the memory controller is configured to
asymmetrically control data transfer between the memory controller and the
one or more buffer units by adjusting a phase of data transmitted by the
memory controller based upon information received from the one or more
buffer units,” as recited in claim 24?
ANALYSIS
Non-statutory obviousness-type double patenting
The Examiner rejects claim 24 under a non-statutory obviousness-type
double patenting rejection as being unpatentable over claims 1–20 of Talbot
’140, with claim 1 of Talbot ’140 being particularly pertinent to claim 24 of
the present application. See Ans. 5–6. Appellant contends the Examiner’s
findings do not show that Talbot ’140 teaches or suggests all of the
recitations of claim 24. See App. Br. 9–10. In particular, Appellant argues
that the Examiner does not show that Talbot ’140 teaches or suggests “a
memory controller . . . coupled to the one or more memory units via the
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parallel interconnect; wherein each of the one or more memory units is
configured to receive a clock signal from the memory controller via one or
more clock signal paths of the parallel interconnect,” as recited in claim 24.
The Examiner responds by correctly noting that dependent claim 10 of
Talbot ’140, which incorporates all the limitations of claim 1 of Talbot ’140,
recites “wherein the parallel interconnect includes one or more clock signal
paths each configured to convey a memory clock signal from the memory
controller to the one or more memory units, wherein the memory clock
signal operates at the second data transfer rate.” Ans. 19. Appellant does
not rebut this finding. See Reply Br. 2.
Appellant does not persuasively distinguish, nor do we readily discern
a distinction, between the recitations in dependent claim 10 of Talbot ’140
and the disputed recitations in claim 24 of the current application.
Therefore, we agree with the Examiner, see Ans. 9, that Talbot ’140 teaches
or suggests “a memory controller . . . coupled to the one or more memory
units via the parallel interconnect; wherein each of the one or more memory
units is configured to receive a clock signal from the memory controller via
one or more clock signal paths of the parallel interconnect,” as recited in
claim 24.
Accordingly, we affirm the Examiner’s non-statutory obviousness-
type double patenting rejection of claim 24, and of claims 25–49, which are
not argued separately with respect to this issue. See App. Br. 9–10.
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35 U.S.C. § 103(a)
The Examiner finds that Osaka teaches or suggests a memory
controller 1 coupled to a plurality of memory modules 20-1 and 20-2 via a
plurality of parallel interconnects, which include clock signal path 30 which
transfers clock signals between the memory controller 1 and the plurality of
memory modules 20-1 and 20-2. See Ans. 8 (citing Osaka, fig. 1 and
¶¶ [0037]–[0040]). Appellant argues that the Examiner erred in rejecting
claim 24 because in Osaka a clock generator source 2 supplies the clock
signal, with memory controller 1 terminating the clock signal path 30 and
absorbing a reflected part of the propagated clock signal. See App. Br. 12.
Appellant argues that because Osaka’s clock generator 2, not memory
controller 1, supplies the clock signal, Osaka fails to teach or suggest
“wherein each of the one or more memory units is configured to receive a
clock signal from the memory controller” (i.e., wherein the memory
controller supplies the clock signal), as recited in claim 24. See id.
In response, the Examiner correctly finds that “Perego discloses a
memory controller providing a clock signal, CCLK 2, to each SL-module
[synchronous link module] via a bus . . . such that the memory controller
comprises a clock generator for providing [a] clock signal to a memory.”
Ans. 20 (citing Perego, fig. 2B). The Examiner continues to rely on Osaka’s
teaching of propagating a clock signal to memory modules via one or more
clock paths of a parallel interconnect. See Ans. 20. Appellant does not
persuasively show error in these findings. See Reply Br. 2 – 4.
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Therefore, we agree with the Examiner, see Ans. 20, that the
combination of Osaka and Perego teaches or suggests the claim 24
recitations directed to a memory controller coupled to the one or more
memory units via the parallel interconnect (as taught by Osaka), wherein
each of the one or more memory units is configured to receive a clock signal
from the memory controller (as taught by Perego) via one or more clock
signal paths of the parallel interconnect (as taught by Osaka).
The Examiner further relies on Osaka’s disclosure of a driver 56,
receiver 57, and location detection circuit 55 to teach or suggest “wherein
the memory controller is configured to asymmetrically control data transfer
between the memory controller and the one or more buffer units by adjusting
a phase of data transmitted by the memory controller based upon
information received from the one or more buffer units,” as recited in claim
24. See id. at 8 – 9 (citing Osaka, ¶¶ [0044]–[0049]). In Osaka, the location
detection circuit 55 finds the difference between a pulse output time from
driver 56 and a time at which the receiver 57 observers the pulse totally
reflected at a buffer 4, where such data can be used for phase adjustment.
See Osaka, ¶ [0048].
Appellant contends the Examiner erred because “the signals relied
upon by the location detection circuit 55 of Osaka are not sent by the buffer
units, but merely reflected back due to the impedance of the input being very
high.” App. Br. 13. Appellant further submits that there is no “two-way
transmission” in Osaka and that “the signals of Osaka are actively sent by
the memory controller, and those same signals are reflected back in a passive
way.” Reply Br. 3. However, we agree with the Examiner that Osaka’s
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detection of a pulse reflected at a buffer 4 for phase adjustment purposes
falls within a broad, but reasonable interpretation of “adjusting a phase of
data . . . based upon information received from the one or more buffer
units.” See Ans. 21 – 22.
Claim 24 does not require the buffer units actively send information to
the memory controller, nor does the Specification define “information
received from the one or more buffer units” in such a way as to require
active transmission. See, e.g., Spec. ¶¶ [0005], [0033], [0049], and [0072].
Instead, the information is merely received from the one or more buffer
units. Information, such as a pulse, reflected from a buffer unit is
information received from the buffer unit, even if the information originated
elsewhere.
Therefore, we agree with the Examiner, see Ans. 8–9, that Osaka
teaches or suggests “wherein the memory controller is configured to
asymmetrically control data transfer between the memory controller and the
one or more buffer units by adjusting a phase of data transmitted by the
memory controller based upon information received from the one or more
buffer units,” as recited in claim 24.
Appellant further contends the Examiner erred because “there is
absolutely no motivation to combine the references as suggested by the
Examiner” and that the Examiner relies on proscribed hindsight reasoning in
rejecting claim 24. See App. Br. 13. However, the Examiner has provided
sufficiently persuasive evidence—including a reason having a rational
underpinning—showing that it would have been obvious to an artisan of
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ordinary skill to combine the teachings and suggestions of Osaka and
Perego. See Ans. 22 (citing Osaka ¶ [0004]). Furthermore, the rejection
takes into account only knowledge which was within the level of an artisan
of ordinary skill at the time of the invention and does not include knowledge
gleaned only from Appellant’s disclosure. In re McLaughlin, 443 F.2d
1392, 1395 (CCPA 1971). Therefore, we agree with the Examiner that the
asserted combination of references is proper under 35 U.S.C. § 103(a).
Accordingly, we sustain the Examiner’s 35 U.S.C. § 103(a) rejection
of claim 24, and of claims 25–49, which are not argued separately with
sufficient specificity with respect to this issue. See App. Br. 14–15; Reply
Br. 3–4.
DECISION
We affirm the Examiner’s decision to reject claims 24–49.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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