Ex Parte Takahashi

Board of Patent Appeals and Interferences

Feb 28, 2008

10785957 (B.P.A.I. Feb. 28, 2008)

UNITED STATES PATENT AND TRADEMARK OFFICE

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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
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Ex parte NAOKI TAKAHASHI
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Appeal 2008-0022
Application 10/785,957
Technology Center 2800
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Decided: February 28, 2008
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Before KENNETH W. HAIRSTON, SCOTT R. BOALICK, and MARC S.
HOFF, Administrative Patent Judges.

HAIRSTON, Administrative Patent Judge.

DECISION ON APPEAL
This is an appeal under 35 U.S.C. §§ 6(b) and 134 from the final
rejection of claims 1 to 5.
Claim 1 is representative of the claimed invention, and it reads as
follows:
1. An oscillator comprising a plurality of logical circuits of a same
type having a same number of input terminals connected in a ring, wherein;
an even number of the logical circuits are connected, and

Appeal 2008-0022
Application 10/785,957

an output node of each logical circuit is connected to an input node of each
logical circuit up to the logical circuit connected to exactly the same number
of input terminals worth of places ahead.1
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Yamaoka US 6,166,572 Dec. 26, 2000
Tang US 6,670,858 B2 Dec. 30, 2003
The Examiner rejected claims 1, 2, and 5 under 35 U.S.C. § 102(e)
based upon the teachings of Tang.
The Examiner rejected claims 3 and 4 under 35 U.S.C. § 103(a) based
upon the teachings of Tang and Yamaoka.
Turning first to the anticipation rejection, Appellant contends that
“[a]lthough Tang arguably discloses a voltage controlled oscillator with
interpolators that create variable delays, Tang fails to disclose, teach or
suggest at least an oscillator comprising a plurality of logical circuits of a
same type as recited in claim 1” (Br. 5).
Tang describes a voltage controlled oscillator (VCO) that connects an
even number of interpolation stages 210 to 240 of the same type and the
same number of input terminals in a ring (Figure 2; col. 3, ll. 16 to 28). The
input and the output nodes of each of the interpolation stages is connected in
exactly the same manner as set forth in claim 1 on appeal (col. 3, ll. 28 to
42).

1 Although the latter portion of this claim limitation is not a model of clarity,
we are able to understand it when it is read in light of the disclosure (e.g.,
Figure 1 and page 8 of the Specification).
2
Appeal 2008-0022
Application 10/785,957

The Examiner contends that “[a]lthough the structure of the
interpolation circuit (210-240) of Tang may be different from the disclosed
logical circuits (i.e., they include a control voltage for adjusting pulse width
of the oscillating signal), the interpolation circuits perform a logical function
by switching between a low state and a high state to create the oscillation for
the oscillation signal” (Ans. 6).
We disagree with the Examiner’s contention that the interpolation
stages 210 to 240 perform a “logical function.” In Tang, an analog summing
of the two input signals to each stage of the oscillator is performed, as
opposed to a logical switching between “a low state and a high state” (col. 4,
ll. 21 to 32). Thus, the anticipation rejection of claims 1, 2, and 5 is reversed
because each and every limitation in the claims is not found either expressly
or inherently in the cited reference to Tang. In re Crish, 393 F.3d 1253,
1256 (Fed. Cir. 2004).
The obviousness rejection of claims 3 and 4 is reversed because the
teachings of Yamaoka fail to cure the noted shortcoming in the teachings of
Tang.
The decision of the Examiner is reversed.
REVERSED

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