Ex Parte Tai et al

Patent Trials and Appeals Board

Apr 12, 2019

14973603 - (D) (P.T.A.B. Apr. 12, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/973,603 12/17/2015
82474 7590 04/16/2019
Morgan, Lewis & Bockius LLP (PH)(SanDisk)
1701 Market Street
Philadelphia, PA 19103-2921
FIRST NAMED INVENTOR
Ying Yu Tai
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
058752-01-5251-US 6812
EXAMINER
VALLECILLO, KYLE
ART UNIT PAPER NUMBER
2112
NOTIFICATION DATE DELIVERY MODE
04/16/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
phpatentcorrespondence@morganlewis.com
judith.troilo@morganlewis.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte YING YU TAI, SEUNG JUNE JEON,
and JIANGLI ZHU
Appeal2018-006854
Application 14/973,603
Technology Center 2100
Before ELENI MANTIS MERCADER, NORMAN H. BEAMER,
and ADAM J. PYONIN, Administrative Patent Judges.
Opinion for the Board filed by Administrative Patent Judge ELENI
MANTIS MERCADER.
Concurring Opinion filed by Administrative Patent Judge NORMAN H.
BEAMER.
MANTIS MERCADER, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appeal 2018-006854
Application 14/973,603
Appellants 1 appeal under 35 U.S.C. § 134(a) from the Examiner's
final rejection of claims 1-21, which constitute all the pending claims in this
application. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
THE INVENTION
Appellants' claimed invention is directed to "performing [] decoding
operations on data obtained from a plurality of units of memory using soft
information values for the plurality of units of memory, where the plurality
of units of memory includes an error correction stripe" and "updating a soft
information value for a first unit of memory" (Abstract).
Independent claim 1, reproduced below, is representative of the
subject matter on appeal:
1. A method performed by a storage device, the method
compnsmg:
at the storage device:
receiving one or more read requests from a host system,
the one or more read requests specifying data stored in a
plurality of units of memory;
obtaining data from the plurality of units of memory in
accordance with the one or more read requests;
performing first decoding operations on the data obtained
from the plurality of units of memory using soft information
values for the plurality of units of memory, wherein the
plurality of units of memory includes an error correction stripe;
1 Appellants identify SanDisk Technologies LLC, which is a subsidiary of
Western Digital Technologies, Inc., as the real party in interest (App. Br. 3).
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determining that two or more of the plurality of units of
memory have uncorrectable errors, wherein the uncorrectable
errors are uncorrectable using the first decoding operations;
updating a respective soft information value for a first
unit of memory in accordance with:
a magnitude of a corresponding soft information
value for a second unit of memory; and
a direction based on parity of the error correction
stripe excluding the first unit of memory, wherein the first unit
of memory and the second unit of memory are included in the
two or more units of memory that have uncorrectable errors;
performing a second decoding operation on data obtained
from at least a portion of the first unit of memory using the
updated soft information value;
in accordance with a determination that the second
decoding operation is successful, providing decoded data from
the second decoding operation to a memory controller; and
in accordance with a determination that the second
decoding operation is unsuccessful, performing a set of
remedial operations or providing an indication of an
irresolvable error condition to a memory controller.
App. Br. 22 (Claims Appendix).
THE REJECTION
The Examiner made the following rejection:
Claims 1-21 stand rejected under 35 U.S.C. § 101 because the
claimed invention is directed to a judicial exception (i.e., a law of nature, a
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Application 14/973,603
natural phenomenon, or an abstract idea) without significantly more. Final
Act. 5-11.
ISSUE
The pivotal issue is whether the Examiner erred in finding the claimed
invention to be directed to a judicial exception without significantly more.
ANALYSIS
Except where indicated, we adopt the Examiner's findings in the
Answer and Final Office Action and we add the following primarily for
emphasis. We note that if Appellants failed to present arguments on a
particular rejection, we will not unilaterally review those uncontested
aspects of the rejection. See Ex parte Frye, 94 USPQ2d 1072, 107 5 (BP AI
2010) (precedential); Hyatt v. Dudas, 551 F.3d 1307, 1313-14 (Fed. Cir.
2008) (the Board may treat arguments Appellant failed to make for a given
ground of rejection as waived).
The Examiner determines the claims are patent ineligible under
35 U.S.C. § 101, because claim 1
recites "receiving one or more read requests from a host system,
the one or more read requests specifying data stored in a
plurality of units of memory; [and] obtaining data from the
plurality of units of memory in accordance with the one or more
read requests." The Examiner finds the claimed "receiving"
read requests and "obtaining data" in accordance with the read
requests is merely data storage and recognition. It is similar to
other concepts that have been identified as abstract by the
courts
(Ans. 4 (alteration in original)). The Examiner additionally finds the
remainder of the limitations of claim 1 (beginning at "performing first
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decoding operations") "describe a process for performing decoding" and that
"standard encoding and decoding, [is] an abstract concept long utilized to
transmit information" (Ans. 5, quoting RecogniCorp, LLC v. Nintendo Co.,
855 F.3d 1322, 1326 (Fed. Cir. 2017) (alteration in original)).
The Examiner further finds when the claim as a whole is analyzed, the
additional elements of a "storage device" and a "memory controller" are
each "recited at a high level of generality" and "[t]hese generic computing
elements alone do not amount to significantly more than the judicial
exception" (Ans. 6).
After the mailing of the Answer and the filing of the Brief in this case,
the US PTO published revised guidance on the application of§ 101 (2019
Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50 (Jan. 7,
2019) (hereinafter "Memorandum")). Under the Memorandum, the Office
first looks to whether the claim recites:
(1) any judicial exceptions, including certain groupings of abstract ideas
(i.e., mathematical concepts, certain methods of organizing human
activity such as a fundamental economic practice, or mental
processes); and
(2) additional elements that integrate the judicial exception into a
practical application (see MPEP § 2106.05(a}-(c), (e}-(h)).
Only if a claim (1) recites a judicial exception and (2) does not integrate that
exception into a practical application, does the Office then look to whether
the claim:
(3) adds a specific limitation beyond the judicial exception that is not
"well-understood, routine, conventional" in the field (see MPEP
§ 2106.05(d)); or
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Application 14/973,603
(4) simply appends well-understood, routine, conventional activities
previously known to the industry, specified at a high level of
generality, to the judicial exception.
See Memorandum.
We agree with the Examiner that the claim is directed to an abstract
idea, and we find that claim 1 recites mental processes that could be
performed in the human mind. Although claim 1 recites a "method
performed by a storage device," the recited steps of
1. "receiving one or more read requests,"
2. "obtaining data,"
3. "performing first decoding operations on the data,"
4. "determining that two or more of the plurality of units of memory
have uncorrectable errors,"
5. "updating a respective soft information value,"
6. "performing a second decoding operation,"
7. "providing decoded data from the second decoding operation to a
memory controller," and
8. "performing a set of remedial operations or providing an indication of
an irresolvable error condition to a memory controller,"
describe operations of observation, evaluation, and judgment, and are
performable mentally or using a pen and paper. Memorandum, 84 Fed. Reg.
at 52; see also RecogniCorp, 855 F.3d at 1326 ("standard encoding and
decoding, an abstract concept long utilized to transmit information").
Other than reciting "to a memory controller," nothing in these claim
limitations precludes the steps from practically performing the decoded
operations in the mind. For example, but for the "to a memory controller"
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language, the claim encompasses the user manually calculating the first and
second decoding operations and manually entering the outcomes to a
memory controller. The mere nominal recitation of a memory controller
does not take the claim limitations out of the mental processes grouping.
Accordingly, claim 1 recites an abstract idea involving mental processes.
If the claim recites an abstract idea, we tum to the second step of the
Alice and Mayo framework ( and, commensurately, Step 2A, Prong Two of
the Guidance), where "we must examine the elements of the claim to
determine whether it contains an "'inventive concept'" sufficient to
'transform' the claimed abstract idea into a patent-eligible application."
Alice Corp. v. CLS Bank Int'!, 573 U.S. 208,221 (2014) (quoting Mayo
Collaborative Servs. v. Prometheus Labs., Inc., 566 U.S. 66, 72-73, 79
(2012)). "A claim that recites an abstract idea must include 'additional
features' to ensure 'that the [claim] is more than a drafting effort designed to
monopolize the [abstract idea]."' Id. (alterations in original) (quoting Mayo,
566 U.S. at 77). "[M]erely requir[ing] generic computer implementation[]
fail[s] to transform that abstract idea into a patent-eligible invention." Id.
Claim 1 recites the limitation of:
updating a respective soft information value for a first unit of
memory in accordance with:
a magnitude of a corresponding soft information
value for a second unit of memory; and
a direction based on parity of the error correction
stripe excluding the first unit of memory, wherein the first unit
of memory and the second unit of memory are included in the
two or more units of memory that have uncorrectable errors.
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This claim limitation integrates the mental process into a practical
application. Specifically, the additional elements recite computer memory
manipulations that cannot be performed by the human mind. Thus, the
claim is eligible because it is not directed to the recited judicial exception.
See Memorandum, Step 2A, Prong Two.
Furthermore, Appellants contend that the claimed invention is akin to
the claimed "computer memory system" held patent-eligible in Visual
Memory LLC v. NVIDIA Corp., 867 F.3d 1253 (Fed. Cir. 2017), because the
claims were directed to "a technological improvement: an enhanced
computer memory system" (App. Br. 12, quoting 867 F.3d at 1259).
Appellants further contend that claim 1 is directed to recovering "data that
would otherwise be lost due to a large number of errors" (App. Br. 14,
quoting Spec. ,r 16), which occur "as the result of various factors affecting
flash memory" (App. Br. 14, quoting Spec. ,r 3).
Appellants further distinguish RecogniCorp by pointing out "[t]he
Federal Circuit held that the claims were patent-ineligible, not simply
because they involve decoding, but because they were directed to a form of
encoding that did not 'improve[] the functioning of a computer."' (App. Br.
16, quoting 855 F.3d at 1327 (emphasis by Appellants)).
We agree with Appellants. Appellants' disclosure indicates that:
[ s Jome embodiments of the present disclosure include a method
of updating soft information values, e.g., used by an LDPC
error encoding and recovery methodology, in order to give the
memory controller another opportunity to decode uncorrectable
data using the primary decoding. The method can recover data
that would otherwise be lost due to a large number of errors,
e.g., random retention errors associated with a storage medium
having one or more die nearing the end of their useful life, and
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random read disturb errors associated with a storage medium
having been intensively read internally or by a host system
(Spec. ,r 17). The recovery of data that would otherwise be lost due to errors
arising in or through use of the storage system integrates the recited judicial
exception into a practical application of that exception. Such data recovery
could increase the lifespan of storage media, as errors associated with
intensive read operations could be corrected. See Memorandum, Step 2A,
Prong Two.
We further agree with Appellants that the technological improvement
described in the disclosure and reflected in the claimed invention is akin to
the "improved computer memory system" found patent-eligible in Visual
Memory, 867 F.3d at 1259. See App. Br. 12-13.
There are no additional elements that need to be considered under
Step 2B as we do not sustain the rejection pursuant to Step 2A, Prong Two.
See Memorandum, 84 Fed. Reg. at 54 ("When the exception is so integrated,
then the claim is not directed to a judicial exception (Step 2A: NO) and is
eligible. This concludes the eligibility analysis.").
Accordingly, we reverse the Examiner's rejection of claims 1-21
under 35 U.S.C. § 101.
CONCLUSION
The Examiner erred in finding the claimed invention to be directed to
a judicial exception without significantly more.
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DECISION
The Examiner's decision rejecting claims 1-21 under 35 U.S.C. § 101
is reversed.
REVERSED
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UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte YING YU TAI, SEUNG JUNE JEON,
and JIANGLI ZHU
Appeal2018-006854
Application 14/973,603
Technology Center 2100
Before ELENI MANTIS MERCADER, NORMAN H. BEAMER,
and ADAM J. PYONIN, Administrative Patent Judges.
BEAMER, Administrative Patent Judge, concurring.
I concur in the result, but conclude that the subject matter of the
claims does not encompass an abstract idea, because it does not fall under
any judicial exception, including certain groupings of abstract ideas (i.e.,
mathematical concepts, certain methods of organizing human activity such
as a fundamental economic practice, or mental processes).
In particular, the record does not establish, and I cannot agree, that
when considered as a whole, these steps are amenable to being performed by
the human mind:
• "receiving one or more read requests from a host system, the
one or more read requests specifying data stored in a plurality
of units of memory";
• "obtaining data from the plurality of units of memory in
accordance with the one or more read requests";
Appeal 2018-006854
Application 14/973,603
• "performing first decoding operations on the data obtained from
the plurality of units of memory using soft information values
for the plurality of units of memory, wherein the plurality of
units of memory includes an error correction stripe";
• "determining that two or more of the plurality of units of
memory have uncorrectable errors, wherein the uncorrectable
errors are uncorrectable using the first decoding operations";
• "updating a respective soft information value for a first unit of
memory in accordance with: a magnitude of a corresponding
soft information value for a second unit of memory; and a
direction based on parity of the error correction stripe excluding
the first unit of memory, wherein the first unit of memory and
the second unit of memory are included in the two or more
units of memory that have uncorrectable errors";
• "performing a second decoding operation on data obtained from
at least a portion of the first unit of memory using the updated
soft information value; in accordance with a determination that
the second decoding operation is successful, providing decoded
data from the second decoding operation to a memory
controller"; and
• "in accordance with a determination that the second decoding
operation is unsuccessful, performing a set of remedial
operations or providing an indication of an irresolvable error
condition to a memory controller."
2