Ex Parte Swei

Patent Trial and Appeal Board

Feb 26, 2016

13237177 (P.T.A.B. Feb. 26, 2016)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/237,177 09/20/2011 Yuwen Swei 2011.0514/1085.839 1091
54657 7590 02/29/2016
DUANE MORRIS LLP (TSMC)
IP DEPARTMENT
30 SOUTH 17TH STREET
PHILADELPHIA, PA 19103-4196
EXAMINER
TRA, ANH QUAN
ART UNIT PAPER NUMBER
2842
MAIL DATE DELIVERY MODE
02/29/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte YUWEN SWEI1
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Appeal 2014-002912
Application 13/237,177
Technology Center 2800
——————
Before ROMULO H. DELMENDO, GEORGE C. BEST, and
CHRISTOPHER L. OGDEN, Administrative Patent Judges.
OGDEN, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1–8, 12–15, 19, and 20 in the above-identified
application. We have jurisdiction pursuant to 35 U.S.C. § 6(b).
We AFFIRM.

1 According to Appellant, the real party in interest is Taiwan Semiconductor
Manufacturing Co., Ltd. Br. 2.
Appeal 2014-002912
Application 13/237,177
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BACKGROUND
Appellant’s invention relates to a supply-independent biasing circuit
such as the embodiment shown in Figure 2, which is reproduced below:

Figure 2 depicts an upper current mirror (transistors M3 and M4) coupled
with a lower current mirror (transistors M1 and M2) designed to produce two
mirrored currents IREF and IOUT which are relatively independent of the
source voltage VDD. See Spec. ¶ 10, 14. In this embodiment, the ratio of
the size (W/L) of M2 to M1 is K, which also sets the ratio of IOUT to IREF.
Id. ¶ 12. The circuit also includes a MOSFET transistor MR that is biased at
the triode region to create a resistance that depends on the gate voltage VG.
Id. ¶ 14–15.
Independent claim 1 is representative:
1. A supply-independent biasing source, comprising:
an upper current mirror including first and second PMOS
transistors;
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a lower current mirror coupled to the upper current
mirror including first and second NMOS transistors, wherein
the first NMOS and first PMOS transistors have drain
terminals coupled together and form a first stack of
transistors and the second NMOS and second PMOS
transistors have drain terminals coupled together and form a
second stack of transistors; and
a first resistive load connected to one of the first and
second stacks, wherein the resistive load comprises a first
MOSFET transistor biased at triode region,
wherein the first MOSFET transistor is sized different
from a transistor of the same polarity from the one of the
first and second stacks to which it is connected and is sized
the same as a transistor of the same polarity from the other
of the first and second stacks.
Br. 19 (emphasis added).
The Examiner maintains the following grounds of rejection:
I. Claims 1, 2, and 192 under 35 U.S.C. § 103(a)3 as being
unpatentable over US 7,372,316 B2 [hereinafter Chatterjee] (issued May 13,
2008) in view of US 2007/0146061 [hereinafter Iriarte] (published June 28,
2007). Final Act. 3–4.
II. Claims 3, 5, 12–15, and 20 under 35 U.S.C. § 103(a) as being
unpatentable over US 7,755,419 B2 [hereinafter Rao] (issued July 13, 2010)
in view of Iriarte and Chatterjee. Final Act. 4–6.
III. Claims 4, 6, 7, 8, and 15 under 35 U.S.C. § 103(a) as being
unpatentable over Chatterjee and Iriarte in combinations with other prior art
references including Rao. Final Act. 6–7.4

2 On page 3, the Final Action incorrectly lists the claims as 3, 5, 12–15, and
20. Br. 9 n.1; Answer 3.
3 35 U.S.C. § 103 (2006).
4 The Examiner has withdrawn additional rejections under 35 U.S.C. §§ 103
and 112, found on pages 2 and 8–11 of the Final Action. See Answer 3.
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Application 13/237,177
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Figure 6 of Chatterjee is reproduced below:

Figure 6 depicts a current source with two current mirrors between two
current branches, see Chatterjee 5:29–7:11, with one current branch attached
to MOS transistor Mt, where “[t]he function desired from transistor Mt is to
provide a controlled resistance,” id. at 7:12–14.
Figures 1 and 2 of Iriarte are reproduced below:

Figure 1 depicts a prior art current source comprising transistors MP1, MP2,
MN1, and MN3, with two current mirrors between two current branches.
See Iriarte ¶ 10. The “second circuit branch,” containing transistors MP2
and MN3, is connected to a resistor R. Id. In addition, “[t]ransistors MN1
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and MN3 are sized in a ratio 1:K. This determines the current of the second
circuit branch.” Id. Figure 2 depicts a circuit similar to Figure 1, except that
“the first circuit branch includes a diode-connected n-channel tail transistor
MN2, and the second circuit branch has a diode-connected n-channel-
transistor MN4 in the place of the resistor R in FIG. 1.” Id. ¶ 12.
Figure 2 of Rao is reproduced below:

Figure 2 depicts a current source comprising transistors P1, P2, N1, and N2,
with two current mirrors between two current branches, and the branch
comprising P2 and N2 is connected to a resistor R1. See Rao 4:34–5:13.
The figure also depicts a “replica leg” comprising transistor P5 and resistor
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R2, the gate of which is connected to the gates of P1 and P2. See id. at
4:43–44.

With respect to the rejection of claims 1, 2, and 19 over Chatterjee in
view of Iriarte, Appellant’s arguments focus solely on claim 1. Br. 9–12.
With respect to the rejection of claims 3, 5, 12–15, and 20 over Rao in view
of Iriarte and Chatterjee, Appellant: (i) notes that claims 3, 5, 12, and 13
depend, either directly or independently, from claim 1 and, therefore, rely on
the same arguments offered for claim 1, id. at 12 ; (ii) provides additional
arguments for claims 5 and 13 as a group, id. at 13–14; and (iii) for claims
14, 15, and 20, relies on the same arguments offered in support of claims 3,
5, 12, 13, and 19, id. at 14–15. As for the remaining grounds of rejection,
Appellant also relies on the arguments in support of claim 1, id. at 15.
Therefore, consistent with the provisions of 37 C.F.R. § 41.37(c)(1)(iv)
(2013), we limit our discussion to claims 1 and 13. That discussion controls
the outcome for all other claims on appeal.
DISCUSSION
Upon consideration of the evidence on this appeal record and each of
Appellant’s contentions raised in the Appeal Brief, we determine that a
preponderance of the evidence supports the Examiner’s conclusion that the
subject matter of Appellant’s claims is unpatentable over the applied prior
art. We sustain the Examiner’s § 103 rejections essentially for the reasons
set out by the Examiner in the Answer. We add the following for emphasis.
The Examiner determines that it would have been obvious for a
person of ordinary skill in the art to combine the circuit described by
Chatterjee, Figure 6, with the teaching in Iriarte that the two transistors
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comprising the second current mirror (MN1 and MN3 in Fig. 1 of Iriarte) are
sized differently in order to specify the current in the branch containing the
resistance. See Final Act. 3. The Examiner also determines that it would
have been obvious to size the connected MOSFET transistor (e.g., Mt in
Chatterjee) the same as “a normal or smallest transistor, for the purpose of
saving space and cost and achieving a desired driving voltage at” the current
node. See id.
Appellant argues, see Br. 11–12, that Chatterjee and Iriarte both teach
away from the limitation in claim 1 specifying that the “first MOSFET
transistor is sized different from a transistor of the same polarity from the
. . . stack[] to which it is connected and is sized the same as a transistor of
the same polarity from the other . . . stack[].” Id. at 19. According to
Appellant, Chatterjee appears to teach:
[E]ach of transistors M1a, M2a and Mt of Chatterjee et
al. FIG. 6 should have different sizes to as to ensure that
the device is first order temperature compensated (i.e.,
some devices have positive coefficients while others have
negative in order to offset (cancel out) one another as
temperature changes).
Id. at 11 (citing Chatterjee 7:21–63). However, as the Examiner correctly
finds, Chatterjee does not place any limitations on the suitable sizes of the
transistors, or that they should be differently sized. Answer 5. Moreover,
Appellant does not explain why one of ordinary skill in the art would have
understood, from a teaching to use both positive and negative temperature
coefficients, that M1a, M2a, and Mt should all be sized differently.
Appellant also argues that Iriarte teaches that “when the resistor R of
FIG. 1 (upon which the Examiner relies) is embodied as a transistor, such as
n-channel transistor MN4 (FIG. 2), that resistor has a different size than both
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MN3 and MN1,” and that this different sizing “provides a reference voltage
that is stable over temperature variations.” Br. 11 (citing Iriarte ¶ 12 and the
different sizing notations in Fig. 2). However, as the Examiner correctly
finds, resistor MN4 in Figure 2 operates as a diode, rather than a resistor.
Answer 5. In addition, Figure 2 of Iriarte also includes a second diode-
connected transistor MN2 on the other current branch. Id. Thus, transistor
MN4 is not functionally equivalent to resistor R in Figure 1 or an equivalent
transistor (such as that described in Chatterjee) that is connected to function
as a resistor. See id.
Therefore, the evidence on this record does not support Appellant’s
argument that either Chatterjee or Iriarte teaches away from the combination
of the two references, and we find no reversible error in the Examiner’s
rejection of claim 1.
Claim 13 requires a third circuit mirror comprising a transistor (e.g.,
M5 in Fig. 2) and a second MOSFET transistor (e.g., MS) that is sized the
same as the first MOSFET transistor (e.g., MR). See Br. 20–22. The
Examiner cites Rao for this limitation, which in Figure 2 depicts a third
circuit branch comprising transistor P5 and resistor R2. See Final Act. 4–5.
The Examiner determines that it would have been obvious for a person of
ordinary skill in the art to combine the teachings of Rao, Iriarte, and
Chatterjee, and to set the sizing of resistances R1 and R2 to be equal to the
size of “a normal or smallest transistor, for the purpose of saving space and
cost and achieving a desired output voltage.” Id.
Appellant argues that Rao teaches that transistor P5 is sized by a
factor of K in relation to the other transistors P1 and P2 to which it is
connected, and therefore Rao teaches that resistance R2 should be different
from resistance R1. See Br. 13–14. Appellant also argues that Rao teaches
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that “‘K’ is greater than one.” Id. at 14 (citing Rao 1:58–61). However, as
the Examiner correctly finds, Rao does not teach that K in Figure 2 should
differ from 1, or that R1 should differ from R2. Answer 7. In the one
example cited by Appellant in which Rao states that K has a specific value,
Rao states that transistors N51 and N52 of Figure 5 “can have the same
channel lengths, but a width of transistor N52 may be ‘K’ times that of N51,
where K is greater than one.” Rao 1:58–61. However, as the Examiner
correctly notes, this discussion concerns the comparative “background art”
example of Rao’s Figure 5, not Figure 2 on which the Examiner relied. See
Answer 7. Transistors N51 and N52 in Figure 5 would correspond to
transistors N1 and N2 of Figure 2, respectively, and are part of the second
current mirror. Thus, the “K” in this context reflects the ratio of the sizing
of the two mirrored current branches in Figure 5, rather than the ratio of
resistances R1 and R2 in Figure 2. Therefore, Appellant does not direct our
attention to any reversible error in the Examiner’s rejection of claim 5.
For the above reasons, and those expressed by the Examiner, we
affirm the Examiner’s decision to reject claims 1–8, 12–15, 19, and 20.
DECISION
The Examiner’s decision is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
AFFIRMED