Ex Parte Sung et al

Patent Trial and Appeal Board

Jul 12, 2018

14452606 (P.T.A.B. Jul. 12, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/452,606 08/06/2014
123187 7590
Williams Morgan, P.C.
710 N. Post Oak Road
Suite 350
Houston, TX 77024
07/13/2018
FIRST NAMED INVENTOR
MinGyuSung
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
GUl00/4014.255600 6597
EXAMINER
GONDARENKO, NATALIA A
ART UNIT PAPER NUMBER
2891
MAIL DATE DELIVERY MODE
07/13/2018 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MIN GYU SUNG, CHANRO PARK,
and HOON KIM
Appeal2017-005896
Application 14/452,606
Technology Center 2800
Before JEFFREY T. SMITH, JAMES C. HOUSEL,
and MICHAEL G. McMANUS, Administrative Patent Judges.
McMANUS, Administrative Patent Judge.
DECISION ON APPEAL
The Examiner finally rejected claims 1-11 of Application 14/452,606
under 35 U.S.C. § 103(a). Final Act. (May 3, 2016) 2-12. Appellant 1 seeks
reversal of these rejections pursuant to 35 U.S.C. § 134(a). We have
jurisdiction under 35 U.S.C. § 6.
For the reasons set forth below, we REVERSE.
1 The Appellant, GLOBALFOUNDRIES, Inc., is identified as the real party
in interest. Appeal Br. 2.
Appeal2017-005896
Application 14/452,606
BACKGROUND
The present application generally relates to a semiconductor
fabrication process having a reduced number of lithography steps. Spec. ,r 4.
The Specification indicates that "[ u ]sing selective etching techniques, a layer
of fill metal is used to protect the dielectric layer in the trenches, eliminating
the need for some lithography steps." Id.
Claim 1 is representative and is reproduced below:
1. A method of forming a semiconductor structure,
compnsmg:
forming an nFET short channel trench (SCT), a pFET
SCT, an nFET long channel trench (LCT), and a pFET LCT in
a dielectric layer that is disposed on a semiconductor substrate;
depositing a high-K dielectric layer in the nFET SCT, the
pFET SCT, the nFET LCT, and the pFET LCT;
depositing an N type work function metal in the nFET
SCT, the pFET SCT, the nFET LCT, and the pFET LCT;
performing a high-K dielectric chamfer process on the
nFET SCT and pFET SCT;
depositing a metal layer in the nFET SCT, the pFET
SCT, the nFET LCT, and the pFET LCT, such that the metal
layer is deposited conformally in the nFET LCT and the pFET
LCT, and wherein the metal layer fills the nFET SCT and the
pFET SCT;
depositing a first organic planarization layer in the nFET
LCT and the pFET LCT;
performing a recess of the metal layer; and
depositing a second organic planarization layer in the
nFET SCT, the pFET SCT, the nFET LCT, and the pFET LCT.
Appeal Br. 23 (Claims App.).
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Appeal2017-005896
Application 14/452,606
REJECTIONS
The Examiner maintains the following rejections:
1. Claims 1--4, 7, and 8 are rejected under 35 U.S.C. § 103(a) as
obvious over Xie2 in view of Liu 3, Fumitake4, and Park5. Final
Act. 2-7.
2. Claim 5 is rejected under 35 U.S.C. § 103(a) as obvious over Xie
in view of Liu, Fumitake, Park, and Shimada 6• Id. at 7.
3. Claim 6 is rejected under 35 U.S.C. § 103(a) as obvious over Xie
in view of Liu, Fumitake, Park, and Saenger 7. Id. at 7-8.
4. Claims 9 and 10 are rejected under 35 U.S.C. § 103(a) as obvious
over Xie in view of Liu, Fumitake, Park, and Bohr8• Id. at 8-11.
5. Claim 11 is rejected under 35 U.S.C. § 103(a) as obvious over Xie
in view of Liu, Fumitake, Park, Bohr, and Chandrashekar9• Id. at
11-12.
DISCUSSION
Rejection 1. Appellant argues that the first rejection is in error on
two bases. First, Appellant argues that the Examiner has not set forth an
2 Xie et al., US 2013/0187236 Al, published July 25, 2013.
3 Liu et al., US 2015/0087144 Al, published Mar. 26, 2015.
4 Fumitake, US 2014/0110778 Al, published Apr. 24, 2014.
5 Park et al., US 2013/0043592 Al, published Feb. 21, 2013.
6 Shimada, US 2005/0095867 Al, published May 5, 2005.
7 Saenger et al., US 2005/0095852 Al, published May 5, 2005.
8 Bohr et al., US 2011/0156107 Al, published June 30, 2011.
9 Chandrashekar et al., US 2013/0302980 Al, published Nov. 14, 2013.
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Appeal2017-005896
Application 14/452,606
adequate reason why a person of ordinary skill in the art would have
combined the teachings of Xie and Liu. Appeal Br. 7-13. Second,
Appellant argues that Fumitake does not teach depositing a metal layer
conformally in the nFET long channel trench (LCT) and pFET LCT. Id. at
14--19.
Reason to Combine the Teachings of Xie and Liu
The Examiner found that Xie teaches a method of forming a
semiconductor having, inter alia, an nFET short channel trench, a pFET
short channel trench, and an nFET long channel trench or a pFET long
channel trench. Final Act. 2.
The Examiner further found that Xie teaches a method that is
applicable to a variety of integrated circuits. Answer 2 ( citing Xie ,r 23 ).
Xie teaches that in one embodiment the devices may have gate lengths on
the order of 40 nm or less [ short channel], and "the completed devices 200N,
200P may be employed in applications requiring high switching speed, e.g.,
microprocessors, memory devices." Xie ,r 26. Similarly, Xie teaches that
wide gate length devices may typically have a relatively large gate length
"and such devices 200W may be employed in applications like high-power
applications, Input/Output circuits, etc." Id.
The Examiner additionally found that Liu teaches "a semiconductor
device (200) that includes a number of gate structures for NFETs and PFETs
including short channel and long channel transistors." Final Act. 3. ( citing
Liu i1 13).
The Examiner determined that one of skill in the art would have
combined the multiple gate structures of Liu with the device of Xie in order
to make an integrated circuit having "a number of gate structures fabricated
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Appeal2017-005896
Application 14/452,606
by high-k dielectric/metal gate last process to have transistors with reduced
gate leakage." Id. at 4. Accordingly, the Examiner determined that the
combination of Xie and Liu would have taught the step of "forming an nFET
short channel trench (SCT), a pFET SCT, an nFET long channel trench
(LCT), and a pFET LCT in a dielectric layer that is disposed on a
semiconductor substrate" as required by claim 1. Id.
Appellant argues that "Liu merely sets forth that nFET and pFET, and
short channel and long channel transistors exist." Reply 2. The mere
existence of such transistors, Appellant argues, does not provide a
motivation to modify the primary reference. Id. Appellant further argues
that high-k gate insulator layers may be used in various settings and "the
teaching or suggestion to use high-k gate insulator layers does not guide the
person of ordinary skill in the art to form all four of an nFET SCT, a pFET
SCT, an nFET LCT, and a pFET LCT in a semiconductor device." Appeal
Br. 1 O; see also Reply Br. 2. Appellant asserts that, if the person of ordinary
skill in the art were to use a high-k gate insulator as opposed to other gate
insulators, he or she could do so without any need or motivation to only do
so in a semiconductor device comprising all four of an nFET SCT, a pFET
SCT, an nFET LCT, and a pFET LCT. Appeal Br. 10-11.
"The combination of familiar elements according to known methods
is likely to be obvious when it does no more than yield predictable results."
KSR Int'! Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Here, the various
gate arrangements are all familiar elements. Liu ,r 13. The combination of
the gate elements of Liu with the remaining elements of Xie does no more
than yield predictable results. Accordingly, Appellant has not shown error
in regard to the combination of the teachings of Xie and Liu.
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Appeal2017-005896
Application 14/452,606
"Depositing a Metal Layer Conformally"
Claim 1 requires depositing a metal layer in each of the four trenches
"such that the metal layer is deposited conformally in the nFET LCT and the
pFET LCT, and wherein the metal layer fills the nFET SCT and the pFET
SCT." Appeal Br. 23 (Claims App.).
The Examiner cites to Figures 4I and 4J of Fumitake in the Final
Rejection. Final Act. 4. These figures are reproduced below for ease of
reference:
l',"],.~X'"/,,w,~ \'',,,,
I' rnn ~ Ll
L ,-"---"---"---"---"--"-"--"-------------"---"---'""-"""-'""-"""J
Figure 4I
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Appeal2017-005896
Application 14/452,606
:_'--.::•::-::-::-:•:".•.• . ....: ... ~
; .
~ r .. , .. -.-)
i
! JOO
:: ::·:~~ .. ~- ' ' \ti~H ~
)
L-.,v., ....... -. ..... ,..,,,,.,_..,.u,,,.,_,..,..,..,._,.,o••...,._.._.._,,..,._..,. ............... ,v.,.-. ........... ,,n•.',",'-'•.,.'·'"''''-"'•'N"""""""".,.,.,. •• .,,.,...,..,,,,,n-.-........ ,,,,.,.,.._-.,,, .. ,,._,,, ...... N~•••''-""-."'N••-.,'-'-"''"n-,, .. .._.,.., .. , ... .,_..,._.,_., ..... ,,v.·.-..-.-.•.·••"''-'- ~
Figure 41
Figures 4I and 4J show cross-sectional views of various stages of a method
for manufacturing a semiconductor device according to the method of
Fumitake.
The Examiner determined that Fumitake "teaches forming a barrier
layer (105) before forming metal layer (106); thus, depositing a metal layer
constitutes adding the barrier layer (105) to have the barrier layer between
the workfunction layer and the filling metal (106)." Answer 7; see also
Final Act. 4.
While there is some ambiguity in the rejection, it is apparent that
barrier layer 105 would not qualify as the "metal layer" of the claim as it is
not taught to be made of metal. See Fumitake ,r 71 (providing that "barrier
layer 105 may be formed of, for example, TiN or TaN."). Nor would metal
layer 106 of Fumitake satisfy the limitation as it is not taught to be deposited
conformally.
The Specification uses the terms "deposits conformally" and "fills" in
the following manner:
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Appeal2017-005896
Application 14/452,606
FIG. 1 Bis a semiconductor structure 100 after a
subsequent process step of depositing a metal layer 130. In
embodiments, metal layer 130 is comprised of tungsten. The
metal layer 130 deposits conformally on the long channel
trenches 126 and 128. However, since the short channel
trenches 122 and 124 are much narrower than the long channel
trenches and have a much higher aspect ratio, the deposition of
metal layer 130 fills the trenches 122 and 124.
Spec. ,r 66.
Figure lB, discussed above, is reproduced here:
Pfff L()
1?f\
1'2.2 i~~·4t { __ ,A __ ~
(-_),._~",---),_\
rt··J .L::::J
I ... ·\..j\
"'"! _____ nt_? ____ t~-------------"
10?.
Figure 1 B is a cross-section of a semiconductor after deposition of metal
layer 130.
It is apparent from the Specification that "deposits conformally"
means to deposit such that the material takes on the shape of the underlying
structure while "fills" means to deposit so that the material does not reflect
the underlying structure. The metal layer 106 of Fumitake "fills" the space
above the barrier layer. It does not conform to the shape of the barrier layer.
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Appeal2017-005896
Application 14/452,606
Accordingly, Appellant has shown reversible error in the Examiner's
determination that Fumitake teaches conformal deposition of a metal layer.
Rejections 2-5. Claims 5, 6, and 9-11 each depend, directly or
indirectly, from claim 1. Appellant relies upon the same arguments put forth
with regard to Rejection 1 in appealing Rejections 2-5 (regarding claims 5,
6, and 9-11). As we have found such arguments (regarding the Fumitake
reference) to be persuasive, we determine that Rejections 2-5 are in error.
CONCLUSION
The rejection of claims 1--4, 7, and 8 as obvious over Xie in view of
Liu, Fumitake, and Park is reversed. The rejection of claim 5 as obvious
over Xie, Liu, Fumitake, Park, and Shimada is reversed. The rejection of
claim 6 as obvious over Xie, Liu, Fumitake, Park, and Saenger is reversed.
The rejection of claims 9 and 10 as obvious over Xie, Liu, Fumitake, Park,
and Bohr is reversed. The rejection of claim 11 as obvious over Xie, Liu,
Fumitake, Park, Bohr, and Chandrshekar is reversed.
REVERSED
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