Ex Parte Stubbs et al

Board of Patent Appeals and Interferences

Nov 30, 2007

11134575 (B.P.A.I. Nov. 30, 2007)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte ERIC T. STUBBS
and JAMES E. MILLER
____________

Appeal 2007-2652
Application 11/134,575
Technology Center 2800
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Decided: November 30, 2007
____________

Before KENNETH W. HAIRSTON, ROBERT E. NAPPI,
and SCOTT R. BOALICK, Administrative Patent Judges.
HAIRSTON, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134 from the final rejection of
claims 1 to 6. We have jurisdiction under 35 U.S.C. § 6(b).
We will sustain the rejection.

Appeal 2007-2652
Application 11/134,575

2
STATEMENT OF THE CASE
Appellants have invented a method of providing an external reference
voltage to a voltage follower circuit that is independent of a power supply
voltage coupled to a memory array of a memory device (Figures 1 and 2;
Spec. 5 and 6).
Claim 1 is representative of the claims on appeal, and it reads as
follows:
1. A method of exchanging data with a memory device having a
memory array, comprising:
receiving an external reference voltage as generated external to the memory
device;
generating on the memory device an internal reference voltage from the
external reference voltage independent of a power supply voltage coupled to
the memory array; and
logically evaluating with the internal reference voltage a logic state of the
data.
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Yuh US 5,646,880 Jul. 8, 1997
The Examiner rejected claims 1 to 6 under 35 U.S.C. § 102(b) based
upon the teachings of Yuh.
Appellants contend that “[c]learly, the Yuh reference describes using
a voltage follower to generate one or more supply voltages, however, the
Yuh reference clearly does not describe the claim elements of ‘receiving an
external reference voltage as generated external to the memory device;
generating on the memory device an internal reference voltage from the
Appeal 2007-2652
Application 11/134,575

3
external reference voltage independent of a power supply voltage coupled
to the memory array’ as recited in Appellants’ independent claim 1” (App.
Br. 6).

ISSUE
Does Yuh receive an externally generated reference voltage that is
independent of a power supply voltage coupled to the memory array?

FINDINGS OF FACT
Yuh describes a semiconductor memory device that includes a
memory cell array 11 (Figure 1; col. 2, ll. 21 to 25). The voltage follower 22
receives a reference voltage VREFL, and generates an internal reference
voltage VINTL from the external reference voltage (Figure 2B; col. 3, ll. 55 to
63). As seen in Figure 4, the external reference voltage VREFL is independent
of the power supply voltage VRTO to a portion of the memory device (col. 4,
ll. 40 to 43). Yuh does not describe any connection between the external
reference voltage VREFL and the power supply voltage VEXT to the pull-up
driver 13 (Figure 1). Yuh uses the internal reference voltage VINTL in the
sensing circuit 16 to logically evaluate a logic state of the data in the
memory (col. 2, l. 57 to col. 3, l. 5).

PRINCIPLES OF LAW
Anticipation is established when a single prior art reference discloses
expressly or under the principles of inherency each and every limitation of
the claimed invention. Atlas Powder Co. v. IRECO, Inc., 190 F.3d 1342,
Appeal 2007-2652
Application 11/134,575

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1347 (Fed. Cir. 1999); In re Paulsen, 30 F.3d 1475, 1478-79 (Fed. Cir.
1994).
ANALYSIS
As indicated supra, Yuh does not describe VREFL as being derived
from either of the two power supply voltages VRTO and VEXT. Thus, we
disagree with Appellants’ argument that the noted reference voltage is not
received as an external reference voltage that is independent of the power
supply voltages (App. Br. 5 and Reply Br. 4).

CONCLUSION OF LAW
Anticipation has been established by the Examiner for claim 1. In
view of the lack of arguments by Appellants directed to claims 2 to 6, we
find that the Examiner has also established anticipation of claims 2 to 6.

ORDER
The anticipation rejection of claims 1 to 6 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

KIS

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