Ex Parte SridharaDownload PDFPatent Trial and Appeal BoardAug 9, 201814679644 (P.T.A.B. Aug. 9, 2018) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 14/679,644 04/06/2015 23494 7590 08/13/2018 TEXAS INSTRUMENTS IN CORPORA TED PO BOX 655474, MIS 3999 DALLAS, TX 75265 UNITED ST A TES OF AMERICA FIRST NAMED INVENTOR Srinivasa Raghavan Sridhara UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. TI-72494.1 3978 EXAMINER BUl,THA-OH ART UNIT PAPER NUMBER 2825 NOTIFICATION DATE DELIVERY MODE 08/13/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): uspto@ti.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte SRINIV ASA RAGHA VAN SRIDHARA Appeal2017-008875 Application 14/679,644 Technology Center 2800 Before GEORGE C. BEST, CHRISTIOPHER L. OGDEN, and JANEE. INGLESE, Administrative Patent Judges. BEST, Administrative Patent Judge. DECISION ON APPEAL The Examiner finally rejected claims 1--4 of Application 14/679,644 under 35 U.S.C. § 103(a) as obvious. Final Act. (March 10, 2016). Appellant1 seeks reversal of these rejections pursuant to 35 U.S.C. § 134(a). We have jurisdiction under 35 U.S.C. § 6. For the reasons set forth below, we affirm. 1 Texas Instruments Inc. is identified as the applicant and real party in interest. Appeal Br. 1. Appeal2017-008875 Application 14/679,644 BACKGROUND The '644 Application relates to static random access memory (SRAM) devices. Spec. ,r 2. In particular, the Specification describes a method for varying the amount of time allowed for signal development on the bit lines of the SRAM device during a read process. See id. ,r 4. Claim 1 is representative of the '644 Application's claims and is reproduced below from the Claims Appendix. 1. An electronic device for testing the signal development time of a selected memory cell in a static random access memory (SRAM) comprising: a single dummy row wherein a first plurality of dummy memory cells are electrically connected to the single dummy row; a single dummy bit line pair comprising a first dummy bit line and a second dummy bit line wherein a second plurality of dummy memory cells is connected to the single dummy bit line pair; a plurality of switches, wherein each switch in the plurality of switches is coupled to a dummy memory cell from the single dummy row and to the single dummy bit line pair; a buffer having at least one input and at least one output; wherein the at least one input is electrically connected to one of the dummy bit lines; wherein the output of the buffer is electrically connected to a sense amp electrically connected to the selected memory cell; wherein a number of dummy memory cells from the single dummy row electrically drive the single dummy bit line pair when the a dummy word line is driven to a logical high value; wherein a word line that is electrically connected to the selected memory cell is driven to a logical high value 2 Appeal2017-008875 Application 14/679,644 concurrently with the dummy word line being driven to a logical high value. Appeal Br. 6 ( emphasis added). REJECTION On appeal, the Examiner maintains the following rejection: Claims 1--4 are rejected under 35 U.S.C. § 103(a) as unpatentable over the combination of Applicant Admitted Prior Art ("AAPA") and Tohata. 2 Final Act. 3. DISCUSSION There are two independent claims on appeal: claims 1 and 3. Appellant presents substantive arguments for reversal of the rejection of claim 1. Appeal Br. 4. Appellant argues that "claim 3 is distinguishable over [the] cited references for at least the same reasons as claim 1." Id. Accordingly, we select claim 1 as representative of the claims on appeal. 37 C.F.R. § 4I.37(c)(l)(iv) (2013). For the following reasons, we affirm the rejection of claim 1. Appellant argues that the rejection of claim 1 should be reversed because the combination of AAP A and Tohata does not describe "a plurality of switches, wherein each switch in the plurality of switches is coupled to a dummy memory cell from a single dummy row and to a single dummy bit line pair." Appeal Br. 4. In rejecting claim 1, the Examiner found that AAP A described each limitation of claim 1 except for the claimed plurality of switches. Final 2 US 7,535,784 B2, issued May 19, 2009. 3 Appeal2017-008875 Application 14/679,644 Act. 3--4. The Examiner further found that Tohata describes a plurality of switches, wherein each switch in the plurality of switches is coupled to a dummy memory cell and to the dummy bit line pair. Id. at 4 ( citing Tohata Figs. 1, 2). Appellant argues that this finding is erroneous. Appeal Br. 4. According to Appellant, "Tohata teaches switches that are electrically connected to separate and distinct dummy bit line pairs; not to the single dummy bit line pair as taught in the invention." Id. This argument is not persuasive. As found by the Examiner, Tohata's Figure 2 shows switches 21 and WNl connected to a single dummy bit line pair consisting of line 16-1 and the "dummy global bit line." See Answer 3; Final Act. 4; see also Tohata Fig. 2. CONCLUSION In view of the foregoing, we affirm the rejection of claims 1--4 of the '644 Application. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). AFFIRMED 4 Copy with citationCopy as parenthetical citation