Ex Parte SotomayorDownload PDFPatent Trial and Appeal BoardDec 22, 201613019912 (P.T.A.B. Dec. 22, 2016) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/019,912 02/02/2011 Guy Sotomayor P9517USX1 (119-0968USX1) 1341 61947 7590 12/27/2016 Ar>r>le - Rlank Rome. EXAMINER c/o Blank Rome LLP DANG, KHANH 717 Texas Avenue, Suite 1400 HOUSTON, TX 77002 ART UNIT PAPER NUMBER 2185 NOTIFICATION DATE DELIVERY MODE 12/27/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): mbrininger @ blankrome. com hou stonpatents @ blankrome .com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte GUY SOTOMAYOR1 Appeal 2015-007493 Application 13/019,912 Technology Center 2100 Before KRISTEN L. DROESCH, JOYCE CRAIG, and MATTHEW J. McNEILL, Administrative Patent Judges. DROESCH, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Appellant seeks review under 35 U.S.C. § 134(a) from the Examiner’ Final Rejection of claims 1, 2, 4—11, 13—20, and 22.2 We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. 1 Appellant indicates the real party in-interest is Apple, Inc. App. Br. 1. 2 Claims 3, 12, and 21 have been objected to as dependent upon a rejected claim but including allowable subject matter. Appeal 2015-007493 Application 13/019,912 BACKGROUND The disclosed invention relates to a system and method for facilitating power management in a multi-core processor. Spec. H 7, 61, Abstract. CLAIMED SUBJECT MATTER Representative claim 1, reproduced from the Claims Appendix of the Appeal Brief, reads as follows (disputed limitations in italics)'. 1. A method for facilitating power management in a multi-core processor, comprising: detecting a change related to a number of active processor cores in the multi-core processor, wherein a given processor core can reside in an active state, wherein the given processor core can draw an active power, or in a constrained state, wherein the given processor core can draw a constrained power, which is less than the active power; in response to detecting the change, computing a new current limit Iccmax for the multi-core processor based on a maximum current that can be supplied to the multi-core processor and the number of active and constrained processor cores; and communicating Iccmax to a power-management mechanism within the multi-core processor, wherein Iccmax causes the power-management mechanism to account for power saved by the constrained processor cores when determining whether to change an operating frequency of the multi-core processor. REFERENCES AND REJECTIONS ON APPEAL Claims 1, 2, 4—7, 10, 11, 13—16, 19, 20, and 22 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Rotem et al. (US 2006/0149975 Al; published July 6, 2006) (“Rotem”) and Burton (US 8,402,294 B2; issued Mar. 19, 2013). 2 Appeal 2015-007493 Application 13/019,912 Claims 8, 9, 17, and 18 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Rotem, Burton, and Durand et al. (US 2004/0221187 Al; published Nov. 4, 2004) (“Durand”). ANALYSIS We have reviewed the Examiner’s rejections in light of Appellant’s arguments in the Brief, the Answer, and the Reply Brief. We are persuaded by Appellant’s arguments. We highlight and address specific findings and arguments below for emphasis. The Examiner relies on Rotem for teaching a method comprising: detecting a change related to a number of active processor cores in the multi-core processor, wherein a given processor core can reside in an active state, wherein the given processor core can draw an active power, or in a constrained state, wherein the given processor core can draw a constrained power, which is less than the active power, as recited in claim 1. Final Act. 2—3 (citing Rotem || 14—21, Fig. 2). The Examiner acknowledges that Rotem does not teach the limitation “in response to detecting the change, computing a new current limit Iccmax for the multi-core processor based on.. .the number of active and constrained processor cores,” as required by claim 1. Final Act. 4. The Examiner finds that Burton teaches “a multiprocessor core 102, wherein the dynamic current for the core is calculated based on the number of active cores and their respective operating frequencies.” Final Act. 4—5 (citing Burton 2:64—3:28, 4:15—42, 5:3—15, 34-43). The Examiner also finds that Burton teaches “calculating a dynamic current for the cores based on a maximum current supplied to the cores.” Final Act. 5 (citing Burton 4:14—60; Figs. 4—5). In the Answer, the Examiner directs attention to the disclosure in Burton related to Figure 4: 3 Appeal 2015-007493 Application 13/019,912 As defined by Burton, column 3, lines 53-67, line 14, the “loadline is a mechanism to linearly lower core voltage when CPU 102 draws large current, which minimizes the power drawn at the maximum CPU current. The loadline also protects against violating a speed-bin voltage (e.g., the minimum voltage at CPU 102 at a given frequency) when CPU 102 goes from zero activity (minimum current) to maximum activity (maximum current) due to a downward spike in voltage” (emphasis added). Ans. 7 (quoting Burton 3:57—64, reproducing Burton Fig. 4); see also Ans. 6 (describing Burton Figure 4). The Examiner finds the aforementioned disclosure related to Figure 4 “is exactly what [is] described in [002[7]] of Appellant’s [Specification, which states that the ‘current limit ICCMAC 111 generally represents a maximum amount of current that can be sourced by power supply 120 without causing an unacceptable voltage drop.” Id. at 7—8 (citing Spec. 127); see also Ans. 3—4, 8 (discussing voltage droop). The Examiner asserts that on the horizontal axis of Burton’s Figure 4, when four processor cores are in operation, the 4-Core Max Icc is a maximum current that can be supplied to the multi-core processor. See Ans. 8. The Examiner further finds that Burton teaches: [i]n detecting a change in a number of processor cores in operation (from four cores to two cores, for example), a 2-Core Max Icc (Fig. 4) or “new current limit” ... is computed based on the 4-Core Max Icc (Fig. 4) or “maximum current that can be supplied to the multi-core processor” . . . and “the number of active and constrained processors cores” ... as shown in Fig. 4, 2 active processor cores and 2 constrained processor cores from a total of 4 processor cores. Ans. 8 (citing Burton 4:14—31). We agree with Appellant’s argument that Burton does not teach or suggest “computing a new current limit Iccmax for the multi-core processor 4 Appeal 2015-007493 Application 13/019,912 based on a maximum current that can be supplied to the multi-core processor and the number of active and constrained processor cores,” as recited in claim 1. See App. Br. 8; Reply Br. 5—6. We agree that Burton instead discloses managing power consumption for the central processing unit (CPU) by setting a voltage for the CPU based on a dynamic current for the CPU, and calculating the dynamic current for the CPU based on the active processing cores in the CPU. See App. Br. at 8—9 (citing Burton 1:42-49, 3:57—60, Abstract, claim 1); see also Burton 3:18—20 (“Power control unit 250 regulates the voltage applied to CPU 102 by power converter 210 .. . .”). We further agree with Appellant’s assertion that the voltage regulation is disclosed in Burton’s Figures 4 and 5, which describe loadlines that represent supply voltages provided to CPU as a function of current. See id. at 9. We agree also with Appellant’s contention that Burton does not disclose computation of a current limit, but merely describes the computation of an actual/dynamic current (i.e., the current that is actually being drawn by the processor), which is not equivalent to a current limit, and is independent of any power supply characteristics. See App. Br. at 10; Reply Br. 6; see also Burton 1:62—64 (“A CPU operating at a given frequency will draw a variable amount of current depending on the type of instructions being executed.”). For these reasons we are constrained to reverse the rejection of claim 1, and independent claims 10, 19, and 22, which recite limitations similar to claim 1, and claims 2, 4—7, 11, 13—16, and 20, dependent therefrom, as unpatentable over Rotem and Burton. As applied by the Examiner, the teachings of Durand do not remedy the deficiencies of Rotem and Burton. See Final Act. 6—7. Accordingly, for the same reasons as claims 1, 2, 4—7, 5 Appeal 2015-007493 Application 13/019,912 10, 11, 13—16, 19, 20, and 22, we reverse the rejection of dependent claims 8, 9, 17, and 18 as unpatentable over Rotem, Burton, and Durand. DECISION We REVERSE the rejections of claims 1, 2, 4—11, 13—20, and 22. REVERSED 6 Copy with citationCopy as parenthetical citation