Ex Parte Sono et al

Board of Patent Appeals and Interferences

Feb 17, 2011

10745465 (B.P.A.I. Feb. 17, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte KOICHI SONO, YOUNG-SUN KIM, and TAE-YOUNG LEE
____________________

Appeal 2009-005799
Application No. 10/745,4651
Technology Center 2600

____________________

Before MAHSHID D. SAADAT, MARC S. HOFF, and
ELENI MANTIS MERCADER, Administrative Patent Judges.

HOFF, Administrative Patent Judge.

DECISION ON APPEAL2

1 The real party in interest is Samsung Electronics Co., Ltd.
2 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or filing a request for rehearing, as
recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE” (paper
delivery mode) or the “NOTIFICATION DATE” (electronic delivery mode)
shown on the PTOL-90A cover letter attached to this decision.

Appeal 2009-005799
Application 10/745,465

STATEMENT OF CASE
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1, 2, 6-9, and 13-17.3 We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
Appellants’ invention concerns apparatus and method for generating a
programmable signal to drive a plasma display panel (PDP) by which data
on the specifications of a PDP that are required to generate a PDP drive
signal are stored in a memory and then appropriately edited so as to be
suitable for the PDP used in order to generate XY drive signals (¶ 13). The
memory stores information to generate a plurality of drive pulse signals
necessary for driving the PDP. A decoder reads information from the
memory and then edits the read information so as to be suitable for
specifications of the PDP. An output waveform generating circuit generates
drive pulse signals corresponding to the information read by the decoder
(Spec. ¶ 14).
Claim 1 is exemplary of the claims on appeal:
1. An apparatus for generating a programmable signal to drive a display
panel, the apparatus comprising:
a memory that stores information to generate a plurality of drive pulse
signals necessary for driving the display panel;
a decoder that reads information stored in an address assigned
according to a predetermined control sequence from the memory, the read
information being suitable for specifications of the display panel; and
an output waveform generating circuit that generates drive pulse
signals corresponding to the information read by the decoder.

The Examiner relies upon the following prior art in rejecting the
claims on appeal:

3 Claims 3-5 and 10-12 stand allowed.
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Application 10/745,465

Tajima US 6,636,187 B2 Oct. 21, 2003
Yamazaki US 7,109,073 B2 Sep. 19, 2006
Claims 1, 2, 8, 9, and 13 stand rejected under 35 U.S.C. § 102(e) as
being anticipated by Tajima.
Claims 6 and 14-17 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Tajima.
Claim 7 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Tajima in view of Yamazaki.
Throughout this decision, we make reference to the Appeal Brief
(“App. Br.,” filed March 4, 2008), the Reply Brief (“Reply Br.,” filed
September 10, 2008) and the Examiner’s Answer (“Ans.,” mailed July 10,
2008) for their respective details.

ISSUE
Appellants argue that the elements of Tajima relied upon by the
Examiner to meet the decoder recited in the claims do not receive data from
memory 47 (Fig. 9) or memory 29 (Fig. 4) (App. Br. 12; Reply Br. 5). In the
Examiner’s view, Tajima teaches that the decoder elements detailed in
Figure 9 are disclosed by Tajima as contained within display data controller
28 of Figure 4, and thus memory 29, also contained within display data
controller 28, outputs to these decoder elements (Ans. 9).
Appellants’ contentions present us with the following issue:
Does Tajima teach a decoder that reads information stored in an
address assigned according to a predetermined control sequence from a
memory?

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FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Tajima
1. Tajima teaches that address generator 451, address selector 453,
and detector 481 are installed in the display data controller 28 of Figure 4
(col. 9, ll. 52-54).
2. Tajima teaches that display data controller 28 stores display data in
the frame memory 29 (col. 7, ll. 37-38).

PRINCIPLES OF LAW
“A rejection for anticipation under section 102 requires that each and
every limitation of the claimed invention be disclosed in a single prior art
reference.” See In re Buszard, 504 F.3d 1364, 1366 (Fed. Cir. 2007)
(quoting In re Paulsen, 30 F.3d 1475, 1478-79 (Fed. Cir. 1994)).
“Section 103 forbids issuance of a patent when ‘the differences
between the subject matter sought to be patented and the prior art are such
that the subject matter as a whole would have been obvious at the time the
invention was made to a person having ordinary skill in the art to which said
subject matter pertains.’” KSR Int'l Co. v. Teleflex Inc., 550 US 398, 405
(2007). The question of obviousness is resolved on the basis of underlying
factual determinations including (1) the scope and content of the prior art,
(2) any differences between the claimed subject matter and the prior art, (3)
the level of skill in the art, and (4) where in evidence, so-called secondary
considerations. Graham v. John Deere Co., 383 U.S. 1, 17-18, 148 USPQ
459, 467 (1966). See also KSR, 550 US at 407 (“While the sequence of these
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questions might be reordered in any particular case, the [Graham] factors
continue to define the inquiry that controls.”)

ANALYSIS
CLAIMS 1, 2, 8, 9, AND 13
Claim 1 recites, inter alia, “a decoder that reads information stored in
an address assigned according to a predetermined control sequence from the
memory” (emphasis added). Claims 8 and 13 recite “reading information
stored in an address assigned according to a predetermined control sequence
from a memory” and “generating drive pulse signals corresponding to the
information read by a decoder” (emphasis added).
The Examiner finds that first address generator 451, address selector
453, scan selector 463, and detector 481 of Tajima, taken together,
correspond to Appellants’ claimed decoder (Ans. 3). Figure 9 illustrates
these elements.
Figure 9 is reproduced below:
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Figure 9 is a block diagram showing a display according to a first
embodiment of the present invention.
In response to Appellants’ argument that the cited elements of Tajima
do not read data from frame memory 47, the Examiner finds that Tajima
teaches that the address generator 451, address selector 453, and detector
481 are installed in the display data controller 28 of Figure 4 (FF 1).
Figure 4, admitted as Prior Art, is reproduced below:
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Figure 4 is a block diagram showing a display employing the PDP of
Figure 1.
The Examiner reasons that because the decoder elements are within
display data controller 28, which contains frame memory 29, the memory
outputs to elements 451, 453, and 481, and also outputs to a driver 23 (Ans.
9).
We disagree with the Examiner’s finding and reasoning. Instead, we
agree with Appellants, who point out that Tajima contains no teaching that
these decoder elements actually read data from frame memory 29 (Reply Br.
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5). Tajima teaches only that display data controller stores display data in the
frame memory 29 (FF 2).
Because Tajima does not teach that its “decoder” reads information
from a memory, as independent claims 1, 8, and 13 require, we find that the
Examiner erred in rejecting claims 1, 2, 8, 9, and 13 under § 102 as being
anticipated by Tajima. We will not sustain the Examiner’s rejection.
CLAIMS 6 AND 14-17
As noted supra, we reverse the rejection of claims 1 and 8, from
which claims 6 and 14-17 variously depend. Because these claims
incorporate the limitations of their parent claims, we will not sustain the
§ 103 rejection of claims 6 and 14-17 for the same reasons set forth with
respect to the § 102 rejection of claims 1 and 8, supra.
CLAIM 7
We have reviewed Yamazaki, and find that it does not supply the
teaching of a decoder that reads information from a memory which we find
supra to be missing from Tajima. Accordingly, we will not sustain the § 103
rejection of claim 7 as unpatentable over Tajima in view of Yamazaki.

CONCLUSION
Tajima does not teach a decoder that reads information stored in an
address assigned according to a predetermined control sequence from a
memory.

ORDER
The Examiner’s rejection of claims 1, 2, 6-9, and 13-17 is reversed.

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Application 10/745,465

REVERSED

ELD
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