Ex Parte Song et alDownload PDFPatent Trial and Appeal BoardSep 8, 201412001186 (P.T.A.B. Sep. 8, 2014) Copy Citation UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/001,186 12/10/2007 Justin Song ITL.1856US (P26642) 2043 47795 7590 09/08/2014 TROP, PRUNER & HU, P.C. 1616 S. VOSS RD., SUITE 750 HOUSTON, TX 77057-2631 EXAMINER ZAMAN, FAISAL M ART UNIT PAPER NUMBER 2111 MAIL DATE DELIVERY MODE 09/08/2014 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte JUSTIN SONG and QIAN DIAO ____________________ Appeal 2012-003958 Application 12/001,1861 Technology Center 2100 ____________________ Before ST. JOHN COURTENAY III, THU ANN DANG, and LARRY J. HUME, Administrative Patent Judges. HUME, Administrative Patent Judge. DECISION ON APPEAL This is a decision on appeal under 35 U.S.C. § 134(a) of the Final Rejection of claims 1–24. We have jurisdiction under 35 U.S.C. § 6(b). We AFFIRM. 1 According to Appellants, the real party in interest is Intel Corporation. App. Br. 3. Appeal 2012-003958 Application 12/001,186 2 STATEMENT OF THE CASE2 The Invention Appellants' invention relates to methods and systems for transitioning a processor package to a low power state. Title. Exemplary Claim Claim 1, reproduced below, is representative of the subject matter on appeal (labels and emphases added to limitations): 1. A method comprising: [a] receiving prediction information regarding utilization of a plurality of cores of a processor package for a next operation interval; [b] setting a delay period for the processor package during the next operation interval based on the prediction information, [b1] wherein during the delay period the processor package is to delay incoming break events and tasks; and [c] causing the processor package to enter into a package low power state for the delay period and thereafter causing the processor package to enter into a package active state for an active period of the next operation interval, [c1] the delay period extending from a beginning of the next operation interval to a beginning of the active period. 2 Our decision relies upon Appellants' Appeal Brief ("App. Br.," filed Aug. 11, 2011); Reply Brief ("Reply Br.," filed Dec. 29, 2011); Examiner's Answer ("Ans.," mailed Oct. 31, 2011); Final Office Action ("Final Act.," mailed Feb. 22, 2011); and the original Specification ("Spec.," filed Dec. 10, 2007). Appeal 2012-003958 Application 12/001,186 3 Prior Art The Examiner relies upon the following prior art as evidence in rejecting the claims on appeal: Storvik, II et al. ("Storvik") US 2004/0098560 A1 May 20, 2004 Belady et al. ("Belady") US 2006/0184287 A1 Aug. 17, 2006 Kardach et al. ("Kardach") US 2007/0005995 A1 Jan. 4, 2007 Stufflebeam US 7,529,956 B2 May 5, 2009 Rejections on Appeal3 R1. Claims 1, 4–6, 9, 10, 17, 19, 21, and 24 stand rejected under 35 U.S.C. § 103(a) as being obvious over the combination of Belady and Kardach. Ans. 4. R2. Claims 2, 3, and 18 stand rejected under 35 U.S.C. § 103(a) as being obvious over the combination of Belady, Kardach and Stufflebeam. Ans. 10. R3. Claims 7 and 8 stand rejected under 35 U.S.C. § 103(a) as being obvious over the combination of Belady, Kardach, and Storvik. Ans. 11. R4. Claims 11–13, 15, and 16 stand rejected under 35 U.S.C. § 103(a) as being obvious over the combination of Belady, Kardach, and Stufflebeam, i.e., the same as rejection R2, supra. Ans. 12. 3 The Examiner has set forth seven (7) separate rejections, but we note rejections R2, R4, and R7 invoke the same combination of references cited, and rejections R3 and R6 are also the same with respect to the combination of references cited. Appeal 2012-003958 Application 12/001,186 4 R5. Claim 14 stands rejected under 35 U.S.C. § 103(a) as being obvious over the combination of Belady, Kardach, Stufflebeam, and Storvik. Ans. 14. R6. Claim 20 stands rejected under 35 U.S.C. § 103(a) as being obvious over the combination of Belady, Kardach, and Storvik, i.e., the same as rejection R3, supra. Ans. 15. R7. Claims 22 and 23 stand rejected under 35 U.S.C. § 103(a) as being obvious over the combination of Belady, Kardach and Stufflebeam, i.e., the same as rejection R2, supra. Ans. 16. GROUPING OF CLAIMS Based on Appellants’ arguments (App. Br. 10–17), we decide the appeal of rejection R1 of claims 1, 4–6, 9, 10, 17, 19, 21, and 24 on the basis of representative claim 1. We address remaining claims in rejections R2–R7, not argued separately, infra. ISSUE Appellants argue (App. Br. 10–17; Reply Br. 1–2) the Examiner's rejection of claims 1, 4–6, 9, 10, 17, 19, 21, and 24 under 35 U.S.C. § 103(a) as being obvious over the combination of Belady and Kardach is in error. These contentions present us with the following issue: Did the Examiner err in finding the cited prior art combination teaches or suggests a method that includes all the limitations of claim 1? Appeal 2012-003958 Application 12/001,186 5 ANALYSIS We only consider those arguments actually made by Appellants in reaching this decision, and we do not consider arguments which Appellants could have made but chose not to make in the Briefs so that any such arguments are deemed to be waived. 37 C.F.R. § 41.37(c)(1)(vii). We disagree with Appellants' arguments with respect to claim 1, and we adopt as our own (1) the findings and reasons set forth by the Examiner in the action from which this appeal is taken and (2) the reasons and rebuttals set forth by the Examiner in the Examiner's Answer in response to Appellants' arguments. However, we highlight and address specific findings and arguments regarding claim 1 for emphasis as follows. With respect to limitation [b], Appellants contend, "there is no disclosure in Belady of the concept of a next operation interval that includes both a delay period and an active period . . . [because] Belady nowhere teaches or suggests a delay of anything." App. Br. 10. Concerning limitation [c1], Appellants further contend Belady "certainly fails to teach or suggest a delay period that extends from a beginning of an operation interval to a beginning of an active period." Id. Appellants also argue with respect to these limitations, Belady simply describes that based on future utilization, one or more processors can be placed into a power savings mode for a given time . . . [but does not teach or suggest] a delay period extending from a beginning of a next operation interval to a beginning of a next active period. And Belady certainly fails to teach or suggest where both of these are part of a next operation interval. App. Br. 11. Appeal 2012-003958 Application 12/001,186 6 Appellants further contend Kardach teaches the opposite of limitation [c1], i.e., "an operation interval having a delay period that is followed by an active period" (id.), because Kardach only teaches "the conventional manner of power management in which a processor is in an active or C0 state at a beginning of an OS tick interval, and thereafter it may be placed into a lower power state." Id. Additionally, Appellants contend Kardach does not teach or suggest limitation [b1], i.e., a processor package that "delay[s] incoming break events and tasks." App. Br. 13. Finally, Appellants contend the prior art combination cited by the Examiner does not teach or suggest the recited processor package includes multiple cores, i.e., limitation [a]. Id. In response, the Examiner finds Belady teaches or at least would have suggested limitation [b] because Belady's power management system 103A determines when processors 2011-4 should be in a power-saving mode, and also when they should be awakened from the power-saving mode based upon a prediction of future utilization. Ans. 17–18; and see Belady ¶¶ 37 and 50; and Fig. 2. As a matter of claim construction of limitation [c1], the Examiner interprets the recited "beginning of the operation interval" as being the time a processor enters the power-saving mode, and the recited "beginning of the active period" as being the time at which the processor exits the power-saving mode and is activated. Id. at 18. We agree with the Examiner's broad but reasonable interpretation. We agree with the Examiner because during examination, a claim must be given its broadest reasonable interpretation consistent with the Specification, as it would be interpreted by one of ordinary skill in the art. Appeal 2012-003958 Application 12/001,186 7 Because the applicant has the opportunity to amend claims during prosecution, giving a claim its broadest reasonable interpretation will reduce the possibility that the claim, once issued, will be interpreted more broadly than is justified. In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Cir. 1984); In re Zletz, 893 F.2d 319, 321 (Fed. Cir. 1989) ("During patent examination the pending claims must be interpreted as broadly as their terms reasonably allow."). In particular, in seeking context for limitation [c1], we note Appellants' Specification discloses: Referring still to FIG. 2, next the processor package may be controlled to be in a package low power state for the idle period (block 130). As will be discussed further below, this low power state may be a deeper low power state than otherwise may be possible. This is so, as the idle period can be a continuous period from the beginning of a next utilization cycle until an active period, which corresponds to the difference between the next utilization cycle length and the idle period length. This control of the processor package may be implemented by receiving OS commands to place the processor package into the selected low power state. Spec. ¶ 34 (emphasis added). Thus, an "active period" may reasonably be interpreted as the period of time equal to the difference between the utilization cycle length and the idle period length. With respect to the recited "operation interval," we note the Specification merely describes such an interval as a period "in which the core is predicted to be in an active state." Spec. ¶ 37. In this case, Appellants' Specification does not provide definitions for either the recited "active period" or "operation interval" that would contradict the Examiner's broad but reasonable construction. Accordingly, Appeal 2012-003958 Application 12/001,186 8 we find no error in the Examiner's interpretation and resulting claim construction. Concerning limitation [b], the Examiner finds, and we agree, "[d]uring the power-saving mode, it would appear to one of ordinary skill in the art that since the processors 2011-4 are in a sleep mode, any tasks that would be directed to those processors 2011-4 would necessarily be delayed." Ans. 18. Further, limitation [b1] recites, "wherein during the delay period the processor package is to delay incoming break events and tasks." The Examiner finds, and we agree, Kardach teaches: "[w]hen the platform enters the nap mode for the current OS tick, platform events and bus cycles are deferred in idle window until the next active window. As with the doze mode, the deferring of interrupts creates a deterministic idle time for devices in the [D0i0] state." In addition, Kardach states that the "platform" includes a processor package, see paragraph 0013. Accordingly, it can be seen that Kardach does in fact teach wherein a processor package delays (i.e., defers) incoming break events (i.e., interrupts) and tasks (i.e., platform events). Ans. 18–19 (citing Kardach ¶ 30). With respect to limitation [a], we note method claim 1 merely recites "receiving prediction information regarding utilization of a plurality of cores of a processor package," but does not positively recite a multicore processor, as Appellants argue. App. Br. 13. We agree with the Examiner's finding (Ans. 19) that Appellants' disclosure does not define the structure or requirements of the claimed "processor package," but instead only shows a group of processor cores. See Spec. Fig. 1, element 50. In light of this disclosure, the Examiner observes Belady's computer cell 200 in Figure 2 Appeal 2012-003958 Application 12/001,186 9 includes multiple processors 2001–4 which each must include at least one core (i.e., corresponding to the claimed “processor package†having “a plurality of cores.â€). The Examiner broadly but reasonably interprets the claimed “processor package†as reading on multiple processors each having at least one core. (Claim 1). Given this construction, the Examiner finds Belady's disclosure teaches or at least would have suggested the recited "processor package," and "a plurality of cores of [the] processor package." Claim 1. We agree with the Examiner's claim construction , analysis, underlying factual findings, and ultimate legal conclusion of obviousness. . Therefore, based upon the findings above, on this record, we are not persuaded of error in the Examiner's reliance on the combined teachings and suggestions of the cited prior art combination to teach or suggest the disputed limitations of claim 1, nor do we find error in the Examiner's resulting legal conclusion of obviousness. Accordingly, Appellants have not provided sufficient evidence or argument to persuade us of any reversible error in the Examiner's reading of the contested limitations on the cited prior art. Therefore, we sustain the Examiner's obviousness rejection of independent claim 1. As Appellants have not provided separate arguments with respect to independent claims 10 and 21, or dependent claims 4–6, 9, and 24, rejected on the same basis as claim 1, we similarly sustain the Examiner's rejection of these claims under 35 U.S.C. § 103(a). While it may appear that Appellants have provided separate arguments directed to overcoming the rejection of independent claims 17 and 19 (App. Br. 14–15), we do not find these arguments to be truly separate Appeal 2012-003958 Application 12/001,186 10 or persuasive. For example, Appellants merely argue, "[t]his rejection is clearly erroneous. This is so at least for similar reasons discussed above as to claim 1." App. Br. 14. Appellants also argue, similar to claim 1, "nothing anywhere [in Belady] teaches or suggests determination of a delay period corresponding to a difference between a length of the next operation interval and a time to service operations scheduled to a core of the processor having a highest predicted utilization rate." App. Br. 15 (emphasis added). In response, the Examiner finds, and we agree: the feature of determining a delay period length can be found in Claim 1 (i.e., “setting the delay period for the processor package during the next operation interval based on prediction information†and “the delay period extending from a beginning of the next operation interval to a beginning of the active periodâ€). Ans. 20. With respect to the recitation of "a core of a multicore processor having a highest predicted utilization rate" (claim 17), we find, in agreement with the Examiner, Belady paragraph 37 teaches or at least suggests: processors 2001–4 are selectively placed in the low power mode for a predetermined amount of time [the claimed “delay periodâ€], and are placed in a normal power mode for another predetermined amount of time which is long enough to service tasks for all of the active cores [which would include the one with the highest predicted utilization]). Ans. 20–21. We agree with the Examiner's claim construction and note, in further support of the Examiner's position, Belady teaches: The method further comprises controlling, by the power management system, power to the resource, based at least in Appeal 2012-003958 Application 12/001,186 11 part on the predicted future utilization of the resource. In one embodiment, the utilization data is collected for a plurality of resources that are operable to perform tasks, and the method further comprises determining, by the power management system, how many of the resources are needed to provide a desired capacity for servicing the predicted future utilization of the resources for performing the tasks. The method further comprises configuring, by the power management system, ones of the resources exceeding the determined number of resources needed to provide the desired capacity in a reduced power- consumption mode. Belady Abstract. Accordingly, Appellants have not shown the Examiner erred in the rejection of claim 17 or dependent claim 19, rejected on the same basis and depending from claim 17. § 103(a) Rejections R2–R7 of Remaining Claims In view of the lack of any substantive or separate arguments directed to the obviousness rejections R2–R7 of claims 2, 3, 7, 8, 11–16, 18, 20, 22, and 23 under § 103 (see App. Br. 15–17),4 we sustain the Examiner's obviousness rejections of these claims, as they fall with their respective independent claims 1, 10, 17, and 21. Arguments not made are considered waived. Our reviewing court states: When the appellant fails to contest a ground of rejection to the Board, section 1.192(c)(7) [(now section 41.37(c)(1)(vii))] imposes no burden on the Board to consider the merits of that ground of rejection . . . [T]he Board may treat any argument with respect to that ground of rejection as waived. See Hyatt v. Dudas, 551 F.3d 1307, 1314 (Fed. Cir 2008). 4 Appellants merely argue these dependent claims are patentable by virtue of their dependency on purportedly allowable base claims. App. Br. 15–17. Appeal 2012-003958 Application 12/001,186 12 Further, when Appellants do not separately argue the patentability of dependent claims, the claims stand or fall with the claims from which they depend. In re King, 801 F.2d 1324, 1325 (Fed. Cir. 1986); In re Sernaker, 702 F.2d 989, 991 (Fed. Cir. 1983). Accordingly, we sustain the rejection of claims 2, 3, 7, 8, 11–16, 18, 20, 22, and 23. REPLY BRIEF To the extent Appellants advance new arguments in the Reply Brief (Reply Br. 1–2) not in response to a shift in the Examiner's position in the Answer, we note that "[a]ny bases for asserting error, whether factual or legal, that are not raised in the principal brief are waived." Ex parte Borden, 93 USPQ2d 1473, 1474 (BPAI 2010) (informative). Cf. with Optivus Tech., Inc. v. Ion Beam Appl'ns. S.A., 469 F.3d 978, 989 (Fed. Cir. 2006) ("[A]n issue not raised by an appellant in its opening brief . . . is waived."). CONCLUSION The Examiner did not err with respect to any of the various obviousness rejections of claims 1–24 under 35 U.S.C. § 103(a) over the combinations of prior art of record, and we sustain the rejections. DECISION We affirm the Examiner's decision rejecting claims 1–24. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2011). AFFIRMED tj Copy with citationCopy as parenthetical citation