Ex Parte so et al

Board of Patent Appeals and Interferences

Aug 19, 2008

10992086 (B.P.A.I. Aug. 19, 2008)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte MYEONG-SEOB SO,
and BYOUNG-DEOG CHOI
____________

Appeal 2008-2488
Application 10/992,086
Technology Center 2800
____________

Decided: August 19, 2008
____________

Before THOMAS A. WALTZ, ROMULO H. DELMENDO, and
KAREN M. HASTINGS, Administrative Patent Judges.

WALTZ, Administrative Patent Judge.

DECISION ON APPEAL
Appellants seek review under 35 U.S.C. § 134 from the Examiner’s
rejections of claims 1, 2, 6-8, 12, and 13 in the final Office Action dated
Appeal 2008-2488
Application 10/992,086

June 2, 20061. This Board has jurisdiction under 35 U.S.C. § 6(b). For the
reasons below, the Examiner’s rejection is affirmed.
The present invention is directed to a thin film transistor (“TFT”)
having channel and gate electrodes made of polysilicon and the source and
drain areas and the gate electrodes comprising specified combinations of n-
type and p-type doping impurities. Claims 1 and 6 are illustrative and
reproduced below:
1. A thin film transistor, comprising:
a semiconductor thin film having a channel area
and n-type or p-type impurity-doped source and
drain areas, the semiconductor thin film formed of
polysilicon;
a gate electrode formed in a position
corresponding to the channel area, the gate
electrode formed of polysilicon;
a gate insulating layer, which insulates the
semiconductor thin film and the gate electrode;
and
source and drain electrodes, which are connected
to each of the source and drain areas of the
semiconductor thin film,
wherein the gate electrode is n-type or p-type
impurity doped with impurities different from the
impurities doped in the source and drain areas for
changing a work function of the gate electrode;
and

1 In the Final Office Action, pending claims 1-3, 5, 6, 8, 9, 12, and 13 were
rejected. In an after-final amendment, filed September 5, 2006, Appellants
cancelled claims 3-5 and 9, as well as amending other pending claims. In an
Advisory Action dated September 25, 2006, the Examiner revised the
rejection of claims 1 and 6 pursuant to 35 U.S.C. § 103(a) rather than §
102(b). Ans. 3.
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Application 10/992,086

wherein a threshold voltage is modulated by
changing a work function difference between the
gate electrode and the semiconductor thin film.

6. A CMOS thin film transistor, comprising:
an NMOS thin film transistor comprising a first
semiconductor thin film having a channel area and
n-type impurity-doped source and drain areas, a
first gate electrode formed in a position
corresponding to the channel area of the first
semiconductor thin film, a first gate
insulating layer, which insulates the first
semiconductor thin film and the first gate
electrode, and first source and drain electrodes,
which are connected to each of the first source and
drain areas of the first semiconductor thin film;
and
a PMOS thin film transistor comprising a second
semiconductor thin film having a channel area and
p-type impurity-doped source and drain areas, a
second gate electrode formed in a position
corresponding to the channel area of the second
semiconductor thin film, a second gate insulating
layer, which insulates the second semiconductor
thin film and the second gate electrode, and second
source and drain electrodes, which are connected
to each of the second source and drain areas of the
second semiconductor thin film,
wherein the first semiconductor thin film, the
second semiconductor thin film, the first gate
electrode, and the second gate electrode are formed
of polysilicon;
the first gate electrode is p-type impurity doped for
changing a work function of the first gate
electrode;
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a threshold voltage of the NMOS thin film
transistor is modulated by changing a work
function difference between the first gate electrode
and the first semiconductor thin film;
the second gate electrode is n-type impurity doped
for changing a work function of the second gate
electrode; and
a threshold voltage of the PMOS thin film
transistor is modulated by changing a work
function difference between the second gate
electrode and the second semiconductor thin film.

The Examiner relies on the following prior art as evidence of
unpatentability:
Reedy 5,895,957 Apr. 20, 1999
Hu US 2004/0227137 A1 Nov. 18, 2004

The following rejection is presented by the Appellants for review:
1. Claims 1-2, 6-8, and 12-13 stand rejected under 35 U.S.C.
§ 103(a) as obvious over Reedy in view of Hu.
FINDINGS OF FACT (FF)
1. Reedy discloses a thin film transistor, left transistor in Fig. 2,
col. 8, ll. 60-65, col. 11, ll. 32-37, comprising a semiconductor thin
film, Fig. 2B (28), col. 11, ll. 32-33, having a channel area, (44), col.
44, l. 20, and inherently with p-type impurity doped source (42S) and
drain (42D) areas.
2. Reedy discloses that the semiconductor thin film is formed of
silicon, col. 11, l. 45, a gate electrode (48) is formed in a position
corresponding to the channel area (apparent in Fig. 2E), the gate
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electrode formed of polysilicon, col. 12, ll. 44, col. 13, l. 46, a gate
insulating layer (40), col. 12, l. 43, which insulates the semiconductor
thin film and the gate electrode; and source and drain electrodes (64),
col. 15, ll. 4-7, which are connected to each of the source and drain
areas of the semiconductor thin film (apparent in Fig. 2E), wherein the
gate electrode is n-type or p-type impurity doped, col. 8, ll. 33-37, col.
14, l. 25, with impurities different from the impurities doped in the
source and drain areas (N-gate on P-channel), col. 13, ll. 64-65, col.
14, ll. 5-6, for changing a work function of the gate electrode, col. 13,
ll. 13-15, 45-47, 58-61; col. 14, ll. 15-16, 32-36; and wherein a
threshold voltage is modulated by changing a work function
difference between the gate electrode and the semiconductor thin film
(inherent in changing the gate electrode work function; col. 13, l. 45 –
col. 14, l. 36).
3. Hu discloses that both P-type and N-type conventional CMOS
thin film transistors (“TFT”) had been known in the art which utilized
polysilicon for the semiconductor thin film (referred to therein as
“polysilicon island 104”). The polysilicon island includes a channel region,
a source region and a drain region. ¶ 0009.
4. Hu discloses that polysilicon thin film transistors had been
studied “with much effort”, and that polysilicon thin film transistors can be
made smaller, increasing the aperture ratio of the pixel [on an LCD display]
and thereby enhancing the brightness of the LCD. Using polysilicon TFTs
in a LCD consumes less energy to achieve the same brightness.
Performance and reliability are improved, and the cost of fabricating a LCD
is lowered when using polysilicon TFTs. ¶ 0006.
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5. Reedy discloses that:
“P+ and N+ polysilicon gate materials, used in
various combinations in N-type MOSFETS and P-
type MOSFETS, are useful in designing and
fabricating digital and analog circuits, voltage
reference circuits and memory type circuits. . . .
The material may be different or the same for each
transistor type . . . depending on the desired
threshold voltage.”
Col. 13, ll. 45-51, 58-60.
PRINCIPLES OF LAW
KSR Int'l Co. v. Teleflex, Inc., 127 S.Ct. 1727, 1734 (2007), states that
“Section 103 forbids issuance of a patent when ‘the differences between the
subject matter sought to be patented and the prior art are such that the
subject matter as a whole would have been obvious at the time the invention
was made to a person having ordinary skill in the art to which said subject
matter pertains.’”
Graham v. John Deere Co., 383 U.S. 1, 17-18 (1966), holds that
the question of obviousness is resolved on the basis of underlying factual
determinations including (1) the scope and content of the prior art, (2) any
differences between the claimed subject matter and the prior art, (3) the level
of skill in the art, and (4) where in evidence, so-called secondary
considerations.
“When a work is available in one field of endeavor, design incentives
and other market forces can prompt variations of it, either in the same field
or a different one. If a person of ordinary skill can implement a predictable
variation, §103 likely bars its patentability. For the same reason, if a
technique has been used to improve one device, and a person of ordinary
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skill in the art would recognize that it would improve similar devices in the
same way, using the technique is obvious unless its actual application is
beyond his or her skill.” KSR, 127 S. Ct. at 1740.
In re Fulton, 391 F.3d 1195, 1201 (Fed. Cir. 2004), holds that “The
prior art's mere disclosure of more than one alternative does not constitute a
teaching away from any of these alternatives because such disclosure does
not criticize, discredit, or otherwise discourage the solution claimed in the
. . . application.”
“A prior art reference teaches away from a combination if it suggests
that the line of development flowing from the reference’s disclosure is
unlikely to be productive of the result sought by applicant.” In re Gurley,
27 F.3d 551, 553 (Fed. Cir. 1994)
The fact that a prior art reference does not expressly disclose a
particular embodiment is not controlling; the question under 35 U.S.C.
§ 103(a) is not what the references expressly teach, but what they would
have suggested to one of ordinary skill in the art at the time the invention
was made. In re Lamberti, 545 F.2d 747, 750 (CCPA 1976).

DISCUSSION
Obviousness over Reedy in view of Hu
The pending claims, 1-2, 6-8 and 12-13, stand rejected under
35 U.S.C. § 103(a) as obvious over Reedy in view of Hu. Appellants only
argue the patentability of claims 1 and 6. See, App. Br. 5-11. Appellants do
not separately argue the patentability of claims 2 and 12, which depend on
claim 1, or of claims 7, 8 or 13, which depend on claim 6. Therefore, we
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treat claims 1, 2, and 12 as a group and claims 6-8 and 13 as a group, with
claims 1 and 6, respectively, as representative of these groups and all other
claims stand or fall together with the representative claims. 37 C.F.R.
§41.37(c)(1)(vii).
Claims 1 and 6
The Examiner rejected Claims 1 and 6 as obvious over Reedy in view
of Hu, finding that Reedy taught all elements of the claimed invention
except that the silicon semiconductor thin film is polysilicon, FFs 1 and 2.
The Examiner found that Hu is analogous art and taught that polysilicon-
based TFTs are widely known due to the advantages of polysilicon over
other forms of silicon in such applications. FF 3. The Examiner then found
Appellants’ invention to be an obvious substitution of the polysilicon TFT of
Hu with the TFT of Reedy. Ans. 5.
Appellants traverse the rejection, first by arguing there is no
motivation in either Reedy or Hu for the substitution, even though they
acknowledge the substitution of polysilicon may be possible. App. Br. 6-8,
Reply Br. 6-7. We disagree. Hu teaches the advantages of using
polysilicon, as known in the art. FF 4. Hu also teaches that use of
polysilicon for the semiconductor thin film (referred to as “polysilicon island
104”) in Hu was already known and practiced in the art. FF 3. “If a
technique has been used to improve one device, and a person of ordinary
skill in the art would recognize that it would improve similar devices in the
same way, using the technique is obvious unless its actual application is
beyond his or her skill.” KSR, 127 S. Ct. at 1740. We determine that one of
ordinary skill in the art would have recognized that the substitution of the
polysilicon island in Hu would improve the device described in Reedy, using
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known techniques. We also determine that Hu provides a motivation for
substituting polysilicon in the thin film transistor of Reedy. FF 4.
Accordingly, we determine that one of ordinary skill would have found that
substitution obvious.
Appellants next traverse the rejection by arguing that substituting the
polysilicon of Hu with the TFT of Reedy would render Reedy unsuitable for
its intended purpose. App. Br. 9-10. We do not find this argument
persuasive, as neither prior art reference suggests that the line of
development flowing from either reference’s disclosure is unlikely to be
productive of the result sought by applicant. Gurley, 27 F.3d at 553. The
fact that the teachings of one reference used in a rejection may not be
optimal with the objectives of another reference in the combination does not
preclude the rejection. “The prior art’s mere disclosure of more than one
alternative does not constitute a teaching away from any of these alternatives
because such disclosure does not criticize, discredit, or otherwise discourage
the solution claimed in the . . . application.” Fulton, 391 F.3d at 1201.
We determine that Appellants have not shown the Examiner has reversibly
erred in combining the references as stated in the Answer.
Claim 6
Appellants further traverse the rejection of claim 6, particularly, over
Reedy and Hu by arguing that Reedy does not teach the particular
combination of p and n doped materials used for the source and drain areas
and for the gate electrode in the PMOS and NMOS. App. Br. 10-11, Reply
Br. 8-11. Appellants describe the examples of various embodiments of the
invention disclosed in Reedy and assert that none teach the present claimed
invention, namely, a CMOS, comprising a PMOS having a p-type impurity-
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doped source and drain area and an n-type impurity-doped gate electrode,
and an NMOS having an n-type impurity-doped source and drain area and a
p-type gate electrode. Id. Even assuming arguendo Appellants’ assessment
of the examples in Reedy is accurate, we find their argument unpersuasive.
The examples of the embodiments in Reedy were not exhaustive of the
teachings overall. See FF 5. We, therefore, find as fact that the general
disclosure in Reedy would have suggested to one of ordinary skill in the art
various combinations of p-type and n-type impurity doped components in
NMOS and PMOS, including that claimed by Appellants. Lamberti,
545 F.2d at 750. Accordingly, we find Appellants have failed to show the
Examiner reversibly erred.
CONCLUSION
For the foregoing reasons, we sustain the rejection of claims 1 and 6,
and of claims 2, 7, 8 and 12-13 by representation, under § 103(a) as obvious
over Reedy in view of Hu.
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
AFFIRMED

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