Ex Parte Smith et al

Board of Patent Appeals and Interferences

Apr 17, 2009

10998187 (B.P.A.I. Apr. 17, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte SHAWN SMITH and STEPHEN R. FORREST
____________

Appeal 2009-1462
Application 10/998,187
Technology Center 2800
____________

Decided:1 April 17, 2009
____________

Before JOSEPH F. RUGGIERO, JOHN A. JEFFERY, and CARLA M.
KRIVAK, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
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2
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-18. We have jurisdiction under 35 U.S.C. § 6(b). We
affirm.

STATEMENT OF THE CASE
Appellants invented a two-component, rectifying junction memory
element for use in write-once, read-many-times (“WORM”) memories. A
first component (1908) serves as both a fuse and a semiconductor, and a
second semiconductor component (1910) forms a rectifying junction with
the first component.2 This structure is shown in Figure 19 of the present
application reproduced below:

Reproduction of Figure 19 of the Present Application Showing Two
Components 1908 and 1910 of the Memory Element

2 See generally Spec. 1:26−2:10; 12:21-27; Abstract; Figs. 19 and 20.
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Claim 1 is illustrative:
1. A two-component memory element comprising:

a first component that serves as both a fuse and a semiconductor; and

a second, semiconductor component that, together with the first
component, forms a rectifying junction.

The Examiner relies on the following as evidence of unpatentability:
Taussig US 6,385,075 B1 May 7, 2002
MacDiarmid US 2002/0083858 A1 Jul. 4, 2002

1. The Examiner rejected claims 1, 6-13, and 16 under 35 U.S.C.
§ 102(b) as anticipated by Taussig (Ans. 3-5).
2. The Examiner rejected claims 2-5, 14, 15, 17, and 18 under 35 U.S.C.
§ 103(a) as unpatentable over Taussig and MacDiarmid (Ans. 6-8).
Rather than repeat the arguments of Appellants or the Examiner, we
refer to the Briefs and the Answer3 for their respective details. In this
decision, we have considered only those arguments actually made by
Appellants. Arguments which Appellants could have made but did not make
in the Briefs have not been considered and are deemed to be waived. See 37
C.F.R. § 41.37(c)(1)(vii).

3 Throughout this opinion, we refer to: (1) the Appeal Brief filed Oct. 25,
2007; (2) the Examiner’s Answer mailed Dec. 31, 2007; and (3) the Reply
Brief filed Mar. 7, 2008.
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THE ANTICIPATION REJECTION
Regarding representative claim 1,4 the Examiner finds that Figures 4
and 5 of Taussig disclose a two-component memory element where one
semiconductor component serves as a fuse, and another semiconductor
component forms a rectifying junction with the first component. Although
the Examiner acknowledges that Taussig discloses a single layer 75 in
Figure 5 that acts as a fuse coupled in series with a diode, the Examiner
notes that layer 75 can be multiple layers. In any event, the Examiner notes
that claim 1 does not recite layers, and a “component” is not necessarily a
layer. As such, the Examiner reasons, a single layer could have two
components and therefore meet the recited limitations. (Ans. 3, 9-11.)
Appellants argue that Taussig does not disclose a memory element
where a rectifying junction is formed between two component,
semiconductor layers. (App. Br. 10.) Although Appellants acknowledge
that (1) Taussig’s Figure 5 shows a semiconductor layer between two
conductors, and (2) Taussig allows for multiple layers of different materials
to be disposed in the semiconductor layer, Appellants nonetheless contend
that Taussig’s rectifying junction is formed between the electrodes and a
single semiconductor layer. (App. Br. 9-10.)

4 Appellants argue claims 1, 6-13, and 16 together as a group. See App. Br.
5-12. Accordingly, we select claim 1 as representative. See 37 C.F.R.
§ 41.37(c)(1)(vii).
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Appellants also argue that even if, for the sake of argument, Taussig
did disclose the recited two-component memory element, the reference
“cannot be asserted to enable any kind of memory element.” According to
Appellants, since Taussig does not disclose or suggest any particular
semiconductor material or component for the layer 75, the reference’s lack
of enablement for a memory element negates anticipation (App. Br. 11-12.)
The issues before us, then, are as follows:

ISSUES
I. Have Appellants shown that the Examiner erred in finding that
Taussig’s semiconductor layer 75 comprises (1) a first component
that serves as both a fuse and a semiconductor, and (2) a second,
semiconductor component that, together with the first component,
forms a rectifying junction in rejecting representative claim 1 under
§ 102?

II. Does Taussig enable the allegedly anticipating subject matter?

FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence:
1. Taussig discloses a memory module 20 including a cross-point
memory array 25 having first and second sets of transverse electrodes 60, 62
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with respective memory elements 26 formed at the crossing points. This
arrangement forms a matrix of memory elements. (Taussig, col. 7, ll. 22-27,
60-67; Figs. 3, 4.)
2. Each memory element 26 comprises a fuse element 64 coupled in
series with a diode element 66. (Taussig, col. 8, ll. 1-7; Fig. 4.) This
characteristic is shown schematically in Taussig’s Figure 4 reproduced
below:

Reproduction of Figure 4 of Taussig Showing Series-Connected Diode
and Fuse Characteristic of Memory Elements 26

3. Figure 5 of Taussig shows a simplified plan view of a cross-point
array memory unit cell. As shown in that figure, the memory comprises two
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layers of orthogonal sets of spaced parallel conductors (i.e., row electrode 62
and column electrode 60) with a semiconductor layer 75 therebetween.
(Taussig, col. 5, ll. 21 and 22; col. 8, l. 61 − col. 9, l. 7; col. 16, ll. 11-13;
Fig. 5.) This arrangement is shown in Taussig’s Figure 5 reproduced below:

Simplified Plan View of a Cross-point Array Memory Unit Cell in
Figure 5 of Taussig

4. Semiconductor layer 75 may comprise multiple layers of different
materials that may not be semiconductors (e.g., metals and dielectrics).
(Taussig, col. 9, ll. 14-21.)
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5. The semiconductor layer may be (1) an amorphous silicon
material, or (2) constructed from one or more organic semiconductor
materials. (Taussig, col. 16, ll. 16-20.)
6. “Where the electrode layers cross, separated by the semiconductor
layer, a rectifying junction is formed between the two electrode conductors.
Each rectifying junction can be considered as a diode in series with a fuse
element . . . .” (Taussig, col. 16, ll. 20-25.)
7. Taussig refers to an “aforementioned” co-pending U.S. patent
application in connection with detailing the processes by which the
integrated circuits (e.g., memory array and addressing circuitry) can be
formed on the substrate, as well as the layers assembled into a memory
module. (Taussig, col. 7, ll. 53-58.)
8. In the Background section, Taussig (1) discusses co-pending U.S.
patent application Serial No. 09/875,356, and (2) incorporates its disclosure
by reference. (Taussig, col. 1, l. 58 − col. 2, l. 8.)
9. U.S. patent application Serial No. 09/875,356 has issued as U.S.
Patent 6,646,912 (“Hurst”).
10. Figures 7 and 8 of Hurst are identical to Figures 4 and 5 of
Taussig.
11. Hurst notes that memory array 25 can be formed according to a
metal-semiconductor-metal (MSM) process. “[This] process results in two
patterned layers of conductive metal circuits with one or more layers of
semiconductor material (possibly incorporating metal and/or dielectric)
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therebetween. Where the metal layers cross and make contact to opposed
sides of the semiconductor layer, a diode junction is formed between the
metal layers.” (Hurst, col. 17, ll. 24-32.)
12. Hurst incorporates by reference International Patent Application
No. WO 99/39394 in connection with describing the production of MSM
diode integrated circuits. (Hurst, col. 17, ll. 32-38.)
13. Hurst notes that “[t]here are many different materials that may be
used for the semiconductor layer of the memory module circuits, some of
which are disclosed in the aforementioned publication [WO 99/39394].”
Hurst also provides examples of inorganic and organic materials that may be
used as semiconductor layers in the memory module. (Hurst, col. 17, l. 39 −
col. 18, l. 6.)
14. In Figure 16, Hurst shows a portion of a memory module circuit
comprising (1) a pair of electrode conductors 70 formed on substrate 50; (2)
two layers of semiconductor material 72, 74 formed on the first metal layer;
and (3) a transverse conductor 76 overlaying the semiconductor layers 72,
74. (Hurst, col. 18, ll. 7-14; Fig. 16.) This structure is shown in Figure 16
of Hurst reproduced below:
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Reproduction of Figure 16 of Hurst Showing Memory Module Circuit
With Semiconductor Layers 72, 74 Between Conductors 70, 76

15. “Where the semiconductor material is sandwiched between the
conductors 70 and 76 of the first and second metal layers, diode elements are
formed.” (Hurst, col. 18, ll. 14-16; Fig. 16.)
16. “Preferably diodes formed by the semiconductor layer(s) in the
memory array act as both the diode (e.g., 66 in FIG. 7) and the fuse (64) of
the memory elements. In this case the semiconductor layer(s) must perform
the function of a fuse . . . .” (Hurst, col. 18, ll. 24-29.)

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PRINCIPLES OF LAW
Anticipation is established only when a single prior art reference
discloses, expressly or under the principles of inherency, each and every
element of a claimed invention as well as disclosing structure which is
capable of performing the recited functional limitations. RCA Corp. v. Appl.
Dig. Data Sys., Inc., 730 F.2d 1440, 1444 (Fed. Cir. 1984); W.L. Gore &
Assoc., Inc. v. Garlock, Inc., 721 F.2d 1540, 1554 (Fed. Cir. 1983).
“A reference anticipates a claim if it discloses the claimed invention
such that a skilled artisan could take its teachings in combination with his
own knowledge of the particular art and be in possession of the invention.”
In re Graves, 69 F.3d 1147, 1152 (Fed. Cir. 1995) (internal citations,
quotation marks, and emphasis omitted).
Even if a claimed invention is disclosed in a printed publication, that
disclosure is insufficient as prior art if it was not enabling. Anticipatory
prior art “must sufficiently describe the claimed invention to have placed the
public in possession of it. . . . Such possession is effected if one of ordinary
skill in the art could have combined the publication's description of the
invention with his own knowledge to make the claimed invention. . . .” In re
Donohue, 766 F.2d 531, 533 (Fed. Cir. 1985) (citations omitted).
It is well settled that “material not explicitly contained in [a] single,
prior art document may still be considered for purposes of anticipation if that
material is incorporated by reference into the document.” Moreover,
“material incorporated by reference is effectively part of the host document
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as if it were explicitly contained therein.” Liebel-Flarsheim Co. v. Medrad,
Inc., 481 F.3d 1371, 1382 n.3 (Fed. Cir. 2007) (internal citations and
quotation marks omitted).

ANALYSIS
We begin our analysis by noting a key distinction regarding
representative claim 1: namely, the distinction between a “component” and a
“layer.” As the Examiner correctly indicates (Ans. 9), claim 1 does not
recite “layers,” but rather more broadly recites “components” which are not
necessarily layers. That is, while a “component” could be a layer, it need
not be so limited in view of term’s scope and breadth.
Nevertheless, even if we assume, without deciding, that Taussig’s
semiconductor layer 75 (FF 3) was limited to a single layer of
semiconductor material (a finding that we do not reach), Taussig would still
fully meet claim 1. First, the semiconductor layer 75 provides the capability
for the memory element to comprise series-connected fuse and diode
elements between the electrodes 60 and 62. See FF 1-3. By virtue of this
arrangement, a rectifying junction is formed between the two electrodes.
(FF 6.)
Second, Taussig notes that the semiconductor layer may comprise one
or more organic semiconductor materials (FF 5; emphasis added). Thus,
there can be multiple semiconductor materials (i.e., “components”) in the
layer. Third, it is axiomatic that forming a rectifying junction (e.g., in the
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nature of a diode) would involve “p-type” and “n-type” semiconductor
regions or materials.5 These respective regions or materials likewise
constitute “components.”
Thus, even assuming that Taussig’s semiconductor layer 75 was one
material (which it does not have to be (FF 5)), ordinarily skilled artisans
would nonetheless have recognized that it would contain n- and p-type
regions to provide the requisite rectifying junction. See FF 6.
As such, nothing in claim 1 precludes the “first component” as
comprising one type of region (e.g., “p-type”), and the “second component”
as comprising the other type of region (e.g., “n-type”) to achieve the recited
functionality. In this case, the “first component” would, at least in part,
serve as both a fuse and a semiconductor, and the “second component”
would form a rectifying junction together with the first component. See FF
2 and 6. We reach this conclusion emphasizing that the claim’s preamble

5 See generally B.G. Yacobi, Semiconductor Materials: An Introduction to
Basic Principles (2003), at 107-110, available at
http://books.google.com/books?id=oeHk_jgqTBYC&pg=PA107&lpg=PA10
7&dq=diode+pn+junction&source=bll&ots=8y65Cw_uDI&sig=PR2CRzAZ
BZacqoi2ktnmLDrFCbk&hl=en&ei=yTXfSbSBGqW8tAOB37C7CQ&sa=
X&oi=book_result&ct=result&resnum=12#PPA107,M1 (last visited Apr.
10, 2009) (describing diodes’ p-n junctions and noting that “[a] p-n junction
is formed between two semiconductor regions of opposite doping types.”).
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recites the open-ended term “comprising” which does not preclude
additional elements.6
While Taussig does not expressly discuss n- and p-type regions or
materials associated with the semiconductor layer 75, the reference
nevertheless anticipates claim 1 since skilled artisans could combine
Taussig’s teachings with their own knowledge of semiconductors and be in
possession of the invention. See Graves, 69 F.3d at 1152. Thus, for this
reason alone, Taussig anticipates claim 1.
Notwithstanding this interpretation, we find that Taussig does, in fact,
envision using multiple semiconductor layers in lieu of a single
semiconductor layer. Taussig all but states this very point. See FF 5.
Taussig further notes that the semiconductor layer 75 may comprise multiple
layers of different materials that may not be semiconductors (e.g., metals and
dielectrics). See FF 4 (emphases added). By indicating that the multiple
layers of different materials may not be semiconductors, the clear
implication is that they may be semiconductors. Taussig’s permissive choice
of words here is telling in this regard, and indeed consistent with other
passages in the disclosure. See, e.g., FF 5.
Nevertheless, the Hurst patent—the disclosure of which is
incorporated by reference in Taussig (FF 7-9)7—all but confirms this point.

6 See Genentech, Inc. v. Chiron Corp., 112 F.3d 495, 501 (Fed. Cir. 1997)
(“‘Comprising’ is a term of art used in claim language which means that the
named elements are essential, but other elements may be added and still
form a construct within the scope of the claim.”) (citation omitted).
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In Figure 16, for example, Hurst shows two semiconductor layers 72, 74
sandwiched between conductors to form diode elements. (FF 14-15.)8
Moreover, Hurst notes that diodes formed by the semiconductor layer(s) in
the memory array act as both the diode and the fuse of the memory elements,
and that the semiconductor layer(s) must perform the function of a fuse in
this situation. (FF 15-16; emphases added.)
The clear import of this discussion is that the semiconductor layers
together form diode elements (i.e., a rectifying junction), and at least one of
the layers form a fuse. Notwithstanding the interpretation noted above
regarding the semiconductors’ p- and n-type regions and material, nothing in
claim 1 precludes these respective semiconductor layers as meeting the
recited first and second “components” respectively. For this additional
reason, we find Taussig anticipates claim 1.
Furthermore, Appellants’ contention that Taussig does not “enable
any kind of memory element” (App. Br. 11-12), let alone the anticipatory
subject matter, is unavailing. In reaching this conclusion, we recognize that

7 It is well settled that “material not explicitly contained in [a] single, prior
art document may still be considered for purposes of anticipation if that
material is incorporated by reference into the document.” Moreover,
“material incorporated by reference is effectively part of the host document
as if it were explicitly contained therein.” Liebel-Flarsheim, 481 F.3d at
1382 n.3 (internal citations and quotation marks omitted).
8 See also FF 11 (noting that “[the MSM] process results in two patterned
layers of conductive metal circuits with one or more layers of semiconductor
material . . . therebetween”) (emphasis added).
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prior art must be enabling to anticipate. Donohue, 766 F.2d at 533. But
Taussig amply meets this requirement. In reaching this conclusion, we note
that the enablement requirement is met so long as ordinarily skilled artisans
could have combined Taussig’s description of the invention with their own
knowledge so as to be in possession of it. See id.
As we indicated above, while Taussig does not expressly discuss n-
and p-type regions or materials associated with the semiconductor layer 75,
skilled artisans could nevertheless have combined Taussig’s teachings with
their own knowledge of semiconductors and be in possession of the
invention. For this reason alone, Taussig enables the anticipatory subject
matter and is a valid anticipatory reference.
In any event, Taussig is replete with teachings that would sufficiently
describe the claimed invention so as to place the public in possession of it.
As we indicated previously, Taussig incorporates by reference the Hurst
disclosure (FF 7-9). Not only is there relevant overlap between these
disclosures (FF 10), Hurst discusses techniques for forming the conductive
metal circuits with one or more layers of semiconductor material
therebetween and provides examples of materials used for the semiconductor
layers (FF 11-16; emphasis added). Hurst also incorporates by reference
another document discussing these production methods and certain
semiconductor materials used (FF 12-13).
In view of this instructive disclosure, Appellants’ allegation that
Taussig does not “enable any kind of memory element” and therefore fails to
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qualify as an anticipatory reference (App. Br. 11-12) is simply belied by the
record before us. We therefore are not persuaded of error in the Examiner’s
reliance on Taussig as an enabled anticipating disclosure.
For the foregoing reasons, Appellants have not persuaded us of error
in the Examiner’s anticipation rejection of representative claim 1.
Therefore, we will sustain the Examiner’s rejection of that claim, and claims
6-13 and 16 which fall with claim 1.9

THE OBVIOUSNESS REJECTION
Regarding the Examiner’s obviousness rejection of representative
claim 2,10 Appellants argue that MacDiarmid does not cure the deficiencies
of Taussig since MacDiarmid does not teach or suggest (1) a rectifying
junction between two two-component memory elements, and (2) any kind of
fuse characteristic or behavior. According to Appellants, MacDiarmid
merely lists semiconductor materials that are used to prepare field-effect-

9 Although Appellants indicate that “claims 6-13 depend from claim 1”
(App. Br. 12), claim 10 is, in fact, independent. While we grouped this
claim with representative claim 1 (and therefore it falls with claim 1), we
note in passing that claim 10 is much broader in scope with respect to the
recited two-component memory elements as compared to claim 1. Compare
claim 10 with claim 1.
10 Appellants argue claims 2-5, 14, 15, 17, and 18 together as a group. See
App. Br. 12-13. Accordingly, we select claim 2 as representative. See
37 C.F.R. § 41.37(c)(1)(vii).
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transistor (FET)-like devices, and has nothing to do with memory devices.
(App. Br. 12-13.)
The Examiner, however, notes that MacDiarmid was cited merely to
teach the specific materials claimed, and that FETs are commonly used as
memory elements. As such, the Examiner reasons, it would have been
obvious to ordinarily skilled artisans to use the materials disclosed by
MacDiarmid in Taussig’s memory element. (Ans. 11-12.)
The issue before us, then, is as follows:

ISSUE
Under § 103, have Appellants shown that the Examiner erred in
combining the teachings of Taussig and MacDiarmid to arrive at the
invention of representative claim 2? This issue turns on whether the
Examiner’s reason to combine the teachings of these references is supported
by articulated reasoning with some rational underpinning to justify the
Examiner’s obviousness conclusion.

FINDINGS OF FACT
The record supports the following additional findings of fact (FF) by a
preponderance of the evidence:
17. MacDiarmid discloses fabrication methods for FET-like devices
including conductive patterns deposited on a substrate. (MacDiarmid,
¶ [0175]; Figs. 32 and 35.)
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18. These devices can be fabricated using different organic and
inorganic semiconductor materials. (MacDiarmid, ¶¶ [0176], [0178].)
19. MacDiarmid notes that one embodiment can include a transistor
where the electrically conductive active material comprises a semi-
conducting polymer deposited on a substrate as at least one of a source,
drain, and connection therebetween. (MacDiarmid, ¶ [0174].)
20. In one embodiment, a programmable read only memory element
is patterned with an aqueous suspension of an poly-3,4-ethylene-
dioxythiophene-polystyrene sulfonate (PEDOT-PSS) onto a substrate.
(MacDiarmid, ¶¶ [0101], [0191].)

PRINCIPLES OF LAW
In rejecting claims under 35 U.S.C. § 103, it is incumbent upon the
Examiner to establish a factual basis to support the legal conclusion of
obviousness. See In re Fine, 837 F.2d 1071, 1073 (Fed. Cir. 1988). In so
doing, the Examiner must make the factual determinations set forth in
Graham v. John Deere Co., 383 U.S. 1, 17 (1966).
Discussing the question of obviousness of claimed subject matter
involving a combination of known elements, KSR Int’l v. Teleflex, Inc., 550
U.S. 398, 127 S. Ct. 1727 (2007), explains:
When a work is available in one field of endeavor, design
incentives and other market forces can prompt variations of it,
either in the same field or a different one. If a person of
ordinary skill can implement a predictable variation, § 103
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likely bars its patentability. For the same reason, if a technique
has been used to improve one device, and a person of ordinary
skill in the art would recognize that it would improve similar
devices in the same way, using the technique is obvious unless
its actual application is beyond his or her skill. Sakraida [v. AG
Pro, Inc., 425 U.S. 273 (1976)] and Anderson's-Black Rock[,
Inc. v. Pavement Salvage Co., 396 U.S. 57 (1969)] are
illustrative—a court must ask whether the improvement is more
than the predictable use of prior art elements according to their
established functions.
KSR, 127 S. Ct. at 1740. If the claimed subject matter cannot be fairly
characterized as involving the simple substitution of one known element for
another or the mere application of a known technique to a piece of prior art
ready for the improvement, a holding of obviousness can be based on a
showing that “there was an apparent reason to combine the known elements
in the fashion claimed.” Id. at 1741. Such a showing requires
“some articulated reasoning with some rational underpinning to
support the legal conclusion of obviousness” . . . . [H]owever,
the analysis need not seek out precise teachings directed to the
specific subject matter of the challenged claim, for a court can
take account of the inferences and creative steps that a person
of ordinary skill in the art would employ.

Id. at 1741 (quoting In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)).
If the Examiner’s burden is met, the burden then shifts to the
Appellants to overcome the prima facie case with argument and/or evidence.
Obviousness is then determined on the basis of the evidence as a whole and
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the relative persuasiveness of the arguments. See In re Oetiker, 977 F.2d
1443, 1445 (Fed. Cir. 1992).

ANALYSIS
We will sustain the Examiner’s obviousness rejection of
representative claim 2. Although MacDiarmid does not teach the particular
type of memory element used by Taussig, we nonetheless see no error in the
Examiner’s reliance on MacDiarmid’s fundamental teaching of using
particular organic semiconductor materials in Taussig’s memory element.
Given that Hurst teaches using a variety of different organic and inorganic
materials for the semiconductor layers in the memory module (FF 13), we
see no reason why ordinarily skilled artisans could not have employed
organic semiconductor materials disclosed by MacDiarmid (FF 18),
particularly in view of MacDiarmid’s varied applications (FF 17-20) which
include a memory element (FF 20).11 On this record, we find the
Examiner’s combining MacDiarmid with Taussig is supported by articulated
reasoning with some rational underpinning to justify the Examiner’s
obviousness conclusion.
Appellants contend that there is nothing in the prior art to suggest that
using the specific mixture recited in claim 3 as both a fuse and one

11 “If a technique has been used to improve one device, and a person of
ordinary skill in the art would recognize that it would improve similar
devices in the same way, using the technique is obvious unless its actual
application is beyond his or her skill.” KSR, 127 S. Ct. at 1740.
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component of a two-component rectifying junction would be predictable or
successful (Reply Br. 10). This argument, however, is directed not to
representative claim 2, but rather to claim 3, and was raised for the first time
in the Reply Brief and is therefore technically waived.12 In any event,
Appellants have not provided evidence to support this assertion.
For the foregoing reasons, Appellants have not persuaded us of error
in the Examiner’s rejection of representative claim 2. Therefore, we will
sustain the Examiner’s rejection of that claim, and claims 3-5, 14, 15, 17,
and 18 which fall with claim 2.

CONCLUSIONS
Appellants have not shown that the Examiner erred in rejecting claims
1, 6-13, and 16 under § 102. Nor have Appellants shown that the Examiner
erred in rejecting claims 2-5, 14, 15, 17, and 18 under § 103.

ORDER
The Examiner’s decision rejecting claims 1-18 is affirmed.

12 See Optivus Tech., Inc. v. Ion Beam Appls. S.A., 469 F.3d 978, 989 (Fed.
Cir. 2006) (“[A]n issue not raised by an appellant in its opening brief ... is
waived.”) (citations and quotation marks omitted).
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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