Ex Parte Singhal

Patent Trials and Appeals Board

Mar 14, 2019

14624323 - (D) (P.T.A.B. Mar. 14, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/624,323 02/17/2015
23494 7590 03/18/2019
TEXAS INSTRUMENTS IN CORPORA TED
PO BOX 655474, MIS 3999
DALLAS, TX 75265
FIRST NAMED INVENTOR
Vipul Kumar Singha!
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
TI-74995 3265
EXAMINER
CHEN,SIBIN
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
03/18/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@ti.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte VIPUL KUMAR SINGHAL
Appeal2018-003978
Application 14/624,323
Technology Center 2800
Before ROMULO H. DELMENDO, JEFFREY R. SNAY, and
MICHAEL G. McMANUS, Administrative Patent Judges.
DELMENDO, Administrative Patent Judge.
DECISION ON APPEAL
The Applicant ("Appellant") 1 appeals under 35 U.S.C. § 134(a) from
the Primary Examiner's final decision to reject claims 1, 6, 7, 9, 10, 12, and
14--19. 2 We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
1 The Appellant is the Applicant, "Texas Instruments Incorporated"
(Application Data Sheet filed February 17, 2015, 4), which, according to the
Brief, is the real party in interest (Appeal Brief filed October 18, 2017
("Br."), 2).
2 Br. 4--10; Final Office Action entered May 22, 2017 ("Final Act."), 2--4;
Examiner's Answer entered December 27, 2017 ("Ans."), 2---6.
Appeal2018-003978
Application 14/624,323
I. BACKGROUND
The subject matter on appeal relates generally to a complementary
metal oxide semiconductor (CMOS) device having an active mode and a
standby mode in order to minimize power consumption (Specification filed
February 17, 2015 ("Spec.") ,r 11) and methods associated therewith (Br. 11,
12).
Annotated Figures 2A and 2B are reproduced from the Drawings filed
February 17, 2015, as follows:
200 ~mu•:.,n """""
/
200 citcc;i;
'·-\ 2; 0 bists ~:e:1t•~f:.ort c,r,:rnt
r·--------a1~s---------
1 GENERATOR
I (OFF) vonc
2~0 .. J 220 -... /
,,.,,.,,ch tI s·,"td, ·r
l
j./ 230:swc!,:h
<)
TONcWELL ..,. ..................... . 1 ......... TO p .. wELL
t
J"-· 250s-si,d,
l
FIG. 2B (stsoot,·)
Figures 2A and 2B above are illustrative embodiments that depict simplified
schematic diagrams representing a circuit 200 for selectively applying body
bias voltage to an N-well and a P-well of a CMOS transistor pair based on
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Appeal2018-003978
Application 14/624,323
whether the device is in an active (Fig. 2A) or standby (Fig. 2B) mode
(Spec. ,r 15). In Figure 2A (active mode), switches 220 and 230 are closed
to couple a bias generation circuit 210 to the CMOS transistor pair's N-well
and P-well in order to apply a forward body bias to the transistor pair and
establish a lower threshold voltage (id.). In addition, in this illustrative
active mode embodiment, switches 240 and 250 are opened to disconnect
the N-well from a voltage supply VDD and the P-well from ground,
respectively (id.). In Figure 2B (standby mode), switches 220 and 230 are
opened to disconnect the bias generation circuit 210, which is turned off for
power savings, from the N-well and the P-well (id. ,r 16). In addition, in this
illustrative standby mode embodiment, switches 240 and 250 are closed to
couple the N-well and P-well to VDD and ground, respectively (id.).
Representative claim 1 is reproduced from the Claims Appendix to the
Appeal Brief, as follows:
1. A complementary metal oxide semiconductor (CMOS)
device having an active mode and a standby mode, the CMOS
device comprising:
a first transistor having a first body;
a second transistor having a second body;
a first forward body bias voltage source that is coupled to
the first body when the CMOS device is in the active mode, and
that is disconnected from the first body when the CMOS device
is in the standby mode;
a second forward body bias voltage source that is coupled
to the second body when the CMOS device is in the active mode,
and that is disconnected from the second body when the CMOS
device is in the standby mode;
a power source coupled to the second body when the
CMOS device is in the standby mode, and disconnected from the
second body when the CMOS device is in the active mode; and
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Appeal2018-003978
Application 14/624,323
a ground coupled to the first body when the CMOS device
is in the standby mode, and disconnected from the first body
when the CMOS device is in the active mode;
wherein the first forward body bias voltage source and the
second forward body bias voltage source are turned off when the
CMOS device is in the standby mode.
(Br. 11; emphasis added.)
II. REJECTION ON APPEAL
On appeal, claims 1, 6, 7, 9, 10, 12, and 14--19 stand rejected under
AIA 35 U.S.C. § I02(a)(2) as anticipated by Boling3 (Ans. 2-6; Final Act.
2--4).
III. DISCUSSION
Although the Appellant provides arguments under separate sub-
headings for the three independent claims on appeal (i.e., claims 1, 9, and
17), the arguments for these claims are essentially the same (Br. 4--10).
Therefore, we confine our discussion to claim 1, which we select as
representative pursuant to 37 C.F.R. § 4I.37(c)(l)(iv). As provided by this
rule, claims 6, 7, 9, 10, 12, and 14--19 stand or fall with claim 1.
The Examiner finds that Boling describes a CMOS device that
includes every limitation recited in claim 1 (Ans. 2-3). In support, the
Examiner relies on Boling's disclosures pertaining to Figures 2A and 2B (id.
(citing Boling ,r,r 40--43)).
The Appellant contends that Boling does not describe the "wherein"
clause highlighted in reproduced claim 1 above (Br. 5). According to the
Appellant, the Examiner is incorrect in finding that the prior art device's
3 US 2016/0026207 Al, published January 28, 2016.
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Appeal2018-003978
Application 14/624,323
state at time t1 equates to a standby mode and the state at time t3 equates to
an active mode (id.). The Appellant argues that, instead, "it can be seen
from [Boling's] Fig. 2B that the clamps are enabled at both times t1 and t3"
and "[t]his means Boling teaches that times t1 and t3 are during ramp up"
(id.; bolding added). Furthermore, the Appellant argues that "there is no
teaching that [Boling's] body bias generator circuits 202-0 and 202-1 are
actually turned off at any point in the operation of the circuit" (id.; bolding
added). The Appellant urges that "VDD [high power supply voltage] is
required for the operation of the bias generator circuit 202-0 and VBP [p-
channel body bias voltage] clamp circuit 204-0 to generate VBP _Gen or
VBP" and that "[a]t time tl, the VBP is clamped to VDD" (id. at 6; bolding
added). The Appellant concludes that, therefore, "VDD is not inactive,
which means body bias generator 202-0 is not turned off at t1 as the
Examiner claims" (id.; bolding added).
The Appellant's arguments fail to identify any reversible error in the
Examiner's rejection. In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011).
Boling describes integrated circuit (IC) devices including MOS-type
transistors for controlling body bias voltages during "[p ]ower-up operations"
(Boling ,r,r 2, 18). According to Boling, these power-up operations "can
include those operations when a power supply voltage initially ramps up,
including when a device is initially powered on, reset, subject to a power
interruption event, or dynamically powered on and off for power
conservation purposes" (id. ,r 18; emphasis added).
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Appeal2018-003978
Application 14/624,323
Boling's Figure 2A is reproduced, as follows:
';/DD!O
........ 2(:8,,1
2[~~2 C:t_.~.MP Gf\.T
'.:'S:S 2\Wl
FIG. 2A
(~ 2!10
II. .
cmL
Boling's Figure 2A above depicts a block schematic diagram for an
exemplary body bias circuit 200 included in an "IC device having a higher
second power supply voltage (VDDIO) that ramps up prior to a first power
supply voltage VDD" (id. ,r 33).
Boling's Figure 2B is reproduced as follows:
c· VDDIO ;---- =----
/ /"".£.. ______ _
I VDD ___ __)
,· \ VBi,,
~ '-------~-------·
~----~----}
FIG.28
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Appeal2018-003978
Application 14/624,323
Boling's Figure 2B above is described as a timing diagram showing a
power-up operation for the circuit depicted in Figure 2A (id. ,r 6).
As shown in Boling's Figure 2B, Boling teaches that, at time tO,
VDDIO begins to ramp up from zero volts, which is the same voltage set for
low power supply voltage VSS (id. ,r,r 40-41), which the Examiner equates
to ground (Ans. 3). Boling teaches that "[a]t about time tl, VDDIO reaches
a level that enables clamp circuits 204-0/1" and "[a]s a result, VBP is
clamped to VDD and VBN is clamped to VSS" (Boling ,r 41). Boling
teaches that "[a]t about time t2, VDD can ramp up" (id. ,r 42). Boling
further teaches that "[a]t about time t3, VDD reaches a desired level for a
predetermined amount of time" and "[a]s a result, clamp control circuit 214
can activate clamp disable signals, resulting in clamp circuits 204-0/1
connecting, or passively enabling the connection of, VBP to VBP_Gen and
connecting, or passively enabling the connection of, VBN to VBN_Gen" (id.
,r 43). Boling teaches that, at this point in time, "[t]he IC can ... operate
with transistors having the desired body bias voltage" (id.).
These disclosures support the Examiner's anticipation findings. As
we found above, Boling teaches that the disclosed operation can be used for
dynamically powering on and off the device for power conservation
purposes (id. ,r 18). Boling teaches that at about time t2, VBP remains
clamped to VDD, thereby preventing any forward biasing of p-channel body
p-njunctions, and "VBN remains clamped to VSS, also preventing the
forward biasing of n-channel body junctions and/or reducing latch-up
conditions" (id. ,r 42). Therefore, we are unpersuaded by the Appellant's
argument that Boling does not describe claim 1 's "wherein" clause
("wherein the first forward body bias voltage source and the second forward
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Appeal2018-003978
Application 14/624,323
body bias voltage source are turned off when the CMOS device is in the
standby mode"). As the Examiner explains (Ans. 4), between times tl-t2,
bias generator circuits 202-0 and 202-1 are not powered because VDD is at
an insufficient voltage level (Fig. 2B, showing VDD at zero volts from tO to
beginning of ramp up at t2 towards VDD_opt (i.e., optimum VDD)) to
power them (Boling ,r 42). According to Boling, it is not until VDD reaches
a sufficient level at about time t3 that clamp control circuit 214 activates
clamp disable signals, thus resulting in connections via clamp circuits 204-
0/1 ofVBP to VBP_Gen and VBN to VBN_Gen (id. ,I 43).
For these reasons, we uphold the Examiner's anticipation rejection as
maintained against claim 1.
IV. SUMMARY
The Examiner's rejection under 35 U.S.C. § 102(a)(2) of claims 1, 6,
7, 9, 10, 12, and 14--19 as anticipated by Boling is sustained. Therefore, the
Examiner's final decision to reject claims 1, 6, 7, 9, 10, 12, and 14--19 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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