Ex Parte Simmons

Patent Trial and Appeal Board

Sep 21, 2017

13627378 (P.T.A.B. Sep. 21, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/627,378 09/26/2012 Michael Simmons 68354.118853 4762
86528 7590 09/25/2017
Slay den Grubert Beard PLLC
401 Congress Avenue
Suite 1900
Austin, TX 78701
EXAMINER
MYERS, PAUL R
ART UNIT PAPER NUMBER
2185
NOTIFICATION DATE DELIVERY MODE
09/25/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
trosson @ sgbfirm.com
patent @ sgbfirm. com
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MICHAEL SIMMONS
Appeal 2017-001604
Application 13/627,378
Technology Center 2100
Before ALLEN R. MacDONALD, JEREMY J. CURCURI, and
ADAM J. PYONIN, Administrative Patent Judges.
MacDONALD, Administrative Patent Judge.
DECISION ON APPEAL
Appeal 2017-001604
Application 13/627,378
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from a final rejection of
claims 1—22. We have jurisdiction under 35 U.S.C. § 6(b).
Illustrative Claims
Illustrative claims 1 and 6 under appeal read as follows (emphasis,
formatting, and bracketing added):
1. A microcontroller comprising:
[A.] a plurality of general purpose input/output (GPIO) ports
each having a plurality of bits each bit having a predefined association
with one of a plurality of external pins;
[B.] a first set of registers being directly programmable and
operable to provide a first GPIO port control and digital data
input/output functionality for all bits of one of the plurality of GPIO
ports through associated external pins;
[C.] a second set of registers being directly programmable and
operable to provide a second GPIO port control and digital data
input/output functionality for all bits of the one of the plurality of
GPIO ports through the associated external pins;
[D.] a multiplexer and associated select register configured to
control the multiplexer to control a GPIO function of any of the
associated external pins of the one of the plurality of GPIO ports
depending on a setting of the select register through either said first or
second register set or at least one of a plurality of peripheral devices
of the microcontroller.
6. An input/output configuration for a processor, comprising:
[A.] a first plurality of registers being directly programmable
and comprising a first general purpose input/output (GPIO)
configuration selectively coupled to associated external pins
representing bits of a GPIO port of the processor;
[B.] a second plurality of registers being directly
programmable and comprising a second general purpose input/output
configuration selectively coupled to the associated external pins; and
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Appeal 2017-001604
Application 13/627,378
[C.] a control register operably coupled to control switching
between the first general purpose input/output configuration and the
second general purpose input/output configuration.
Rejection on Appeal
The Examiner rejected claims 1—22 under 35 U.S.C. § 103(a) as being
unpatentable over Microchip DS70058D (“Section 11. I/O Ports”; Microchip
Technology Inc.; 2005)(hereinafter “DS70058D”).
Appellant’s Contentions1
1. Appellant contends that the Examiner erred in rejecting claim 1
under 35 U.S.C. § 103(a) because
DS70058D fails to teach the limitation of claim 1 that “a second
set of registers being directly programmable and operable to
provide a second GPIO port control and digital data input/output
functionality for all bits of the one of the plurality of GPIO ports
through the associated external pins.” As stated above in
DS70058D peripherals take over the control of assigned pins and
do not allow a user to directly control the pins as such a function
is reserved to the PIO modules.
App. Br. 10 (emphasis added).
2. Appellant further contends that the Examiner erred in rejecting
claim 1 under 35 U.S.C. § 103(a) because:
The provision of two sets of registers that can
independently be selected to perform an I/O port function is not
a mere duplication of parts but allows a user to control an
external pin, e.g. by two different software routine without the
necessity to first save the content of a current setting of a first
routine and restore it after its execution. Rather an efficient
1 These contentions are determinative as to the rejection on appeal.
Therefore, Appellant’s other contentions are not particularly discussed
herein.
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Appeal 2017-001604
Application 13/627,378
switch is possible by the provision of a second set of control
registers as provided by a microcontroller according to the
independent claims, wherein an I/O pin can perform the
respective function of a second routine by simply switching from
the first set to the second set. No “context saving” of the I/O port
is necessary. Hence, contrary to the examiner's conclusion, the
specific structure as claimed is not a mere duplication of parts.
App. Br. 10-11.
Issue on Appeal
Did the Examiner err in rejecting claim 1 as being obvious?
ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellant’s
arguments that the Examiner has erred.
As to Appellant’s above contentions 1 and 2, we agree. We conclude,
consistent with Appellant’s argument, there is insufficient articulated
reasoning to support the Examiner’s findings that the reference renders
obvious two sets of registers which are directly programmable. Therefore,
we conclude that there is insufficient articulated reasoning to support the
Examiner’s final conclusion that claim 1 would have been obvious to one of
ordinary skill in the art at the time of Appellant’s invention. See Final Act. 5.
CONCLUSIONS
(1) Appellant has established that the Examiner erred in rejecting
claims 1—22 as being unpatentable under 35 U.S.C. § 103(a).
(2) On this record, these claims have not been shown to be
unpatentable.
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Appeal 2017-001604
Application 13/627,378
DECISION
The Examiner’s rejection of claims 1—22 is reversed.
REVERSED
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