Ex Parte Shiraiwa et al

Board of Patent Appeals and Interferences

Jul 18, 2011

11469164 (B.P.A.I. Jul. 18, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/469,164 08/31/2006 Hidehiko Shiraiwa AF02054 6070
22898 7590 07/19/2011
LAW OFFICES OF MIKIO ISHIMARU
2055 GATEWAY PLACE
SUITE 700
SAN JOSE, CA 95110
EXAMINER
NGUYEN, KHIEM D
ART UNIT PAPER NUMBER
2823
MAIL DATE DELIVERY MODE
07/19/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte HIDEHIKO SHIRAIWA, YOUSEOK SUH,
HARPREET SACHAR, and SATOSHI TORII
____________

Appeal 2009-010383
Application 11/469,164
Technology Center 2800
____________

Before MARC S. HOFF, CARLA M. KRIVAK, and THOMAS S. HAHN,
Administrative Patent Judges.

KRIVAK, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

Appeal 2009-010383
Application 11/469,164

2
STATEMENT OF THE CASE
Appellants’ claimed invention is a manufacturing method for a non-
volatile memory system having a protection layer (Spec. 1:4-5).
Independent claim 1 is reproduced below:
1. A memory manufacturing method comprising:
forming a memory gate stack, having a charge trap layer,
over a semiconductor substrate;
forming a protection layer of a single conformal layer and
uniform thickness on the charge trap layer; and
forming a protection enclosure for the charge trap layer with
the protection layer and the memory gate stack.

REJECTIONS
The Examiner rejected claims 1-3, 5-13, and 15-20 under 35 U.S.C.
§ 102(b) based upon the teachings of Shiraiwa (US 6,740,605 B1).
The Examiner rejected claims 4 and 14 under 35 U.S.C. § 103(a)
based upon the teachings of Shiraiwa and Lingunis (US 6,933,219 B1).

ANALYSIS
The Examiner finds Shiraiwa teaches all the features of Appellants’
claimed invention. Particularly, the Examiner finds Shiraiwa teaches a
protection layer formed of a single conformal layer and uniform thickness on
a charge trap layer as claimed.
Appellants assert Shiraiwa teaches a protection layer 42 formed on a
spacer 40 and an electrode 24 (Fig. 10) and thus the protection layer is not in
direct contact with the charge trap layer 30, as claimed. Appellants state the
term “on” is defined in their Specification as “there is direct contact among
elements” (Spec. 5:1-2; Br. 13). Accordingly, Appellants argue there needs
Appeal 2009-010383
Application 11/469,164

3
to be direct contact between the charge trap layer and the protection layer.
Shiraiwa does not teach or suggest any direct contact. The Examiner merely
responds that “‘on’ does not mean there is a direct contact among elements”
and under a broadest reasonable interpretation “on” can mean a layer is
formed above or over another layer “regardless of other elements
sandwiched therebetween” (Ans. 14).
Because of the specific meaning disclosed at page 5 of the
Specification, Appellants’ term “on” must be given the meaning asserted by
Appellants (Br. 12). Thus, since there is no direct contact between
Shiraiwa’s protection layer and the charge tap layer, Shiraiwa does not
anticipate Appellants’ claimed invention.
Claims 4 and 14 depend from independent claims 1 and 11,
respectively. Lingunis does not cure the deficiencies of Shiraiwa. Thus,
these claims are not obvious over the cited combination.

DECISION
The Examiner’s decision rejecting claims 1-20 is reversed.

REVERSED

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