Ex Parte Shidla et al

Board of Patent Appeals and Interferences

Aug 26, 2009

10328906 (B.P.A.I. Aug. 26, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte DALE J. SHIDLA, ANDREW H. BARR, and
JACKY TSUN-YAO CHANG

____________________

Appeal 2009-009005
Application 10/328,906
Technology Center 2100
____________________

Decided: August 26, 2009
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Before LEE E. BARRETT, ST. JOHN COURTENAY, III, and
THU A. DANG, Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION ON APPEAL

I. STATEMENT OF CASE
Appellants appeal the Examiner’s final rejection of claims 1-22 under
35 U.S.C. § 134(a) (2002). We have jurisdiction under 35 U.S.C. § 6(b)
(2002).
We affirm.
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A. INVENTION
According to Appellants, the invention relates to a method for
providing automatic detection of different microprocessor architectures
within a system (Spec. 28, ll. 8-9).

B. ILLUSTRATIVE CLAIM
Claim 9 is exemplary and reproduced below:

9. A system comprising:

a microprocessor socket for receiving a first
microprocessor or a second microprocessor, wherein said first
microprocessor comprises a first architecture and said second
microprocessor comprises a second architecture, wherein said
first architecture of said first microprocessor is different from
said second architecture of said second microprocessor;

a chipset comprising:

a first architecture support hardware associated with said
first architecture; and

a second architecture support hardware associated with
said second architecture; and

a selector module coupled to said microprocessor socket,
said chipset, said first architecture support hardware, and said
second architecture support hardware, said selector module
automatically determining whether said first architecture of said
first microprocessor or said second architecture of said second
microprocessor is coupled to said microprocessor socket, and
said selector module automatically activating said first
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architecture support hardware when said first architecture of
said first microprocessor is automatically determined as being
coupled with said microprocessor socket and automatically
activating said second architecture support hardware when said
second architecture of said second microprocessor is
automatically determined as being coupled with said
microprocessor socket.

C. REJECTIONS
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Reeves US 5,918,023 Jun. 29, 1999
Talbot US 6,516,373 B1 Feb. 4, 2003
Anandakumar US 6,574,213 B1 Jun. 3, 2003
Nova US 2003/0114885 A1 Jun. 19, 2003
Andric US 6,707.684 B1 Mar. 16 2004
Liu US 6,804,292 B2 Oct. 12, 2004
Okin US 7,043,585 B2 May 9, 2006

Claims 1, 3, 5, 7, and 8 stand rejected under 35 U.S.C. § 102(b) as
anticipated by Reeves.
Claims 2 and 6 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Reeves in view of Talbot.
Claim 4 stands rejected under 35 U.S.C. § 103(a) as unpatentable over
Reeves in view of Official Notice.1
Claims 9-10 and 14-22 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Talbot in view of Official Notice and Nova.

1 The Appeal Brief’s and Examiner Answer’s stated grounds of rejection
(App. Br. 8; Ex. Ans. 3) fail to specify that the rejections of claims 4 and 9-
22 rely on Official Notice.
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Claims 11-13 stand rejected under 35 U.S.C. § 103(a) as unpatentable
over Talbot, Nova, and Official Notice in view of Okin.

II. ISSUES
1) Have Appellants shown that the Examiner erred in finding that
Reeves anticipate the invention of claim 1? In particular, the issue turns on
whether Appellants’ general allegation of patentability meets Appellants’
burden of showing the Examiner’s errors.
2) Have Appellants shown that the combination of Talbot in view
of Official Notice and Nova neither teaches nor would have suggested “said
selector module automatically activating said first architecture support
hardware when said first architecture of said first microprocessor is
automatically determined as being coupled with said microprocessor socket
and automatically activating said second architecture support hardware when
said second architecture of said second microprocessor is automatically
determined as being coupled with said microprocessor socket,” as recited by
claim 9? In particular, the issue turns on whether Talbot teaches or suggests
an automatic determination of which processor architecture is coupled to its
system and an according activation of processor architecture support.

III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.

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Appeal Brief
1) The Appeal Brief asserts Reeves as teaching that “each
processor has its own working voltage and must be properly connected” and
then merely identifies (underlines) portions of claim 1 as being “in contrast”
to that asserted teaching (App. Br. 10-11).
Talbot
2) Talbot discloses a motherboard that receives, via a connector,
either of two processor modules having different processor architectures
(col. 2, ll. 32-47).
3) An architecture identifier signal is transmitted from a mounted
processor module to the motherboard to identify the architecture of the
mounted processor module (col. 2, l. 48 – col. 3, l. 4).
4) The architecture identifier signal activates a respective one of
two Basic Input/Output System (BIOS) ROM for the processor modules,
such that the appropriate initialization program is read out of the activated
ROM to render the motherboard compatible with the mounted processor
module (col. 3, l. 66 – col. 4, l. 16).

IV. PRINCIPLES OF LAW
Claim Interpretation
The claims measure the invention. See SRI Int’l v. Matsushita Elec.
Corp., 775 F.2d 1107, 1121 (Fed. Cir. 1985) (en banc). “[T]he PTO gives
claims their ‘broadest reasonable interpretation.’” In re Bigio, 381 F.3d
1320, 1324 (Fed. Cir. 2004) (quoting In re Hyatt, 211 F.3d 1367, 1372 (Fed.
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Cir. 2000)). “Moreover, limitations are not to be read into the claims from
the specification.” In re Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993)
(citing In re Zletz, 893 F.2d 319, 321 (Fed. Cir. 1989)).
35 U.S.C. § 102
Our reviewing court has determined that “[t]eaching away is
irrelevant to anticipation.” See Seachange International, Inc., v. C-Cor, Inc.,
413 F.3d 1361, 1380 (Fed. Cir. 2005).
Official Notice
An adequate traverse of the Examiner’s taking of Official Notice must
contain adequate information or argument to create on its face a reasonable
doubt regarding the circumstances justifying the Examiner’s notice of what
is well known to one of ordinary skill in the art. In re Boon, 439 F.2d 724,
728 (CCPA 1971).
New Arguments
“[I]t is inappropriate for appellants to discuss in their reply brief
matters not raised in … the principal brief[ ]. Reply briefs are to be used to
reply to matter[s] raised in the brief of the appellee.” Kaufman Company v.
Lantech, Inc., 807 F.2d 970, 973 n.* (Fed. Cir. 1986). “Considering an
argument advanced for the first time in a reply brief … is not only unfair to
an appellee … but also entails the risk of an improvident or ill-advised
opinion on the legal issues tendered.” McBride v. Merrell Dow and
Pharms., Inc., 800 F.2d 1208, 1211 (D.C. Cir. 1986) (internal citations
omitted).

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V. ANALYSIS
35 U.S.C. § 102(b)
Claims 1, 3, 5, 7, and 8; Reeves
Regarding claim 1, Appellants argue that “the rejection of Claims 1, 3,
5, 7, and 8 are [sic] improper as the rejection of Claims 1, 3, 5, 7 and 8 does
not satisfy the requirements of a prima facie case of obviousness under 35
U.S.C. § 102(b)” (App. Br. 9). Appellants further argue that Reeves
“teaches away” from the claimed features “since Reeves clearly teaches and
anticipates the importance of the very specific connection and the different
termination resistors requiring the importance of the proper connection”
(App. Br. 11; Appellants’ emphasis). However, prima facie obviousness and
teaching away are issues arising under 35 U.S.C. § 103(a). They do not
arise under 35 U.S.C. § 102. See Seachange International, Inc., v. C-Cor,
Inc., 413 F.3d 1361, 1380 (“[t]eaching away is irrelevant to anticipation”).
Thus, these arguments are inapplicable to this rejection under 35 U.S.C. §
102.
Furthermore, in support of their arguments, Appellants assert Reeves
as teaching that “each processor has its own working voltage and must be
properly connected,” and then underline portions of claim 1 as being “in
contrast” to that teaching (App. Br. 10-11). The general allegation of
patentability does not specify, as required, how the underlined language of
claim 1 patentably distinguishes the claimed invention over Reeves (Id.).
This form of argument is wholly ineffective in demonstrating error in the
Examiner’s prima facie case to establish the patentability of the claims on
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appeal. See Ex parte Belinne, Appeal No. 2009-004693, decided August 10,
2009, (BPAI) (informative). Available at:
http://www.uspto.gov/web/offices/dcom/bpai/its/fd09004693.pdf
We find such general allegation of patentability does not meet
Appellants’ burden. See 37 C.F.R. § 1.111(b).
In the Reply Brief, Appellants set forth a new argument that
“Appellants understand Reeves to be limited to the disclosure of ‘[b]oard
100 can receive either two 200, or two 202, or one 200 and one terminator
board, or one 202 and one terminator board’ (Examiner’s Answer; page 16,
lines 8-9).” (Reply Br. 2). However, this new argument was not raised by
the Appeal Brief, and we will not consider it on this appeal. See Kaufman,
807 F.2d at 973 and McBride, 800 F.2d at 1211.
Accordingly, we conclude that Appellants have not shown that the
Examiner erred in rejecting claim 1 and claims 3, 5, 7, and 8 falling with
claim 1 as anticipated by Reeves under 35 U.S.C. § 102(b).
35 U.S.C. §103(a)
Claims 2 and 6; Reeves and Talbot
Appellants contend that claims 2 and 6 are allowable in view of their
dependence on claim 1 (App. Br. 12). As discussed above with respect to
claim 1, Appellants have not shown that the Examiner erred in rejecting
claim 1 as anticipated by Reeves. Accordingly, we conclude that Appellants
have also not shown that the Examiner erred in rejecting claims 2 and 6 over
the teachings of Reeves in view of Talbot under 35 U.S.C. § 103(a).
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Claim 4; Reeves and Official Notice
Regarding dependent claim 4, in response to the Examiner’s apparent
taking of Official Notice that “[i]t is generally known in the art that the
bridge can be within [sic] chipset” (Ex. Ans. 17) and the Examiner’s
submission of several references to “provide enough basis that chipsets
comprising northbridge and southbridge chips is [sic] well known in the art”
(Id.), Appellants argue that “the claimed embodiments as provided in Claim
4 are not considered to be typical, as asserted by the Office Action” (App.
Br. 13).
To adequately traverse the Examiner’s finding of Official Notice,
Appellants’ traversal must contain information or argument that is adequate
to create, on its face, a reasonable doubt as to the circumstances justifying
the Examiner’s notice. See In re Boon, 439 F.2d at 728. Appellants must
specifically point out the supposed errors in the Examiner's action, which
would include stating why the noticed fact is not considered to be common
knowledge or well-known in the art. See 37 C.F.R. § 1.111(b). See also
MPEP § 2144.03. Here, Appellants do not state why the noticed fact is not
considered common knowledge or well-known in the art and do not provide
information or argument creating a reasonable doubt that it was well known
in the art to arrange a bridge within a chipset. Thus, Appellants have not
adequately traversed the Official Notice.
Accordingly, Appellants have not shown that the Examiner erred in
rejecting claim 4 over the teachings of Reeves in view of Official Notice
under 35 U.S.C. § 103(a).
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Claims 9-10 and 14-22; Talbot, Nova, and Official Notice
Appellants provide the same arguments with respect to independent
claims 9 and 16. Therefore, we select claim 9 as being representative of the
cited claims. 37 C.F.R. § 41.37(c)(1)(vii). Regarding independent claim 9,
Appellants argue that “the combination of Talbot in view of Nova do not
provide ‘automatic determination of which processor is in which slot and
activating the support hardware accordingly’, instead, as stated in the
previous Office Action, Talbot in view of Nova merely act as a selector”
(App. Br. 16). However, according to the Examiner, Talbot discloses an
architecture identifier signal used to recognize different types of mounted
processor modules and discloses an according activation of support
hardware (Ex. Ans. 18).
Appellants’ argument that the references do not provide “automatic
determination of which processor is in which slot” is not commensurate with
the claimed invention. That is, claim 9 recites only one “microprocessor
socket,” i.e., only one slot. Contrary to Appellants’ argument, since claim 9
recites only one socket/slot, it does not require an automatic determination
of which processor is in “which slot.”
Thus, we address on appeal whether Talbot in view of Official Notice
and Nova teach and/or would have suggested “said selector module
automatically activating said first architecture support hardware when said
first architecture of said first microprocessor is automatically determined as
being coupled with said microprocessor socket and automatically activating
said second architecture support hardware when said second architecture of
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said second microprocessor is automatically determined as being coupled
with said microprocessor socket” (claim 9). This issue turns on whether
Talbot teaches or suggests an automatic determination of which processor
architecture is coupled to its system and an according activation of processor
architecture support.
Talbot discloses a motherboard that can receive either of two
processor modules having different processor architectures (FF 2). The
processor architecture of the mounted processor module is identified by an
architecture identifier signal, which is provided by the mounted processor
module to the motherboard (FF 3). The architecture identifier signal
activates a respective one of two Basic Input/Output System (BIOS) ROM
for the processor modules (FF 4). The appropriate initialization program is
transferred out of the activated ROM, which corresponds to the mounted
processor module, to render the motherboard compatible with the
architecture of the mounted processor module (FF 4).
A skilled artisan would have understood the use of the architecture
identifier signal, to determine which type of processor module is mounted,
as an automatic determination of which processor architecture is coupled to
the motherboard. A skilled artisan would have understood the use of the
architecture identifier signal to activate the appropriate BIOS ROM, i.e.,
corresponding to the mounted processor module, as an according activation
of architecture support hardware. Thus, a skilled artisan would have
understood Talbot as teaching and/or suggesting an automatic determination
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of which processor architecture is coupled to a system and an according
activation of processor architecture support.
Appellants further argue, for the reasons stated with respect to claim
4, the Examiner has improperly taken Official Notice that a bridge is
typically arranged within a chipset (App. Br. 16). Again, Appellants have
not stated why the noticed fact is not considered common knowledge or
well-known in the art and have not provided information or argument
creating a reasonable doubt that it was well known in the art to arrange a
bridge within a chipset. As with claim 4, Appellants merely argue that the
embodiment of claim 9 is not typical (Id.). Such an argument does not
satisfy Appellants’ burden.
Accordingly, we conclude that Appellants have not shown that the
Examiner erred in rejecting claim 9 and claims 10 and 14-22 falling with
claim 9 over the teachings of Talbot in view of Official Notice and Nova
under 35 U.S.C. § 103(a).
Claims 11-13; Talbot, Nova, Official Notice, and Okin
Claims 11-13 depend from claim 9. Appellants contend that claims
11-13 are allowable in view of their dependence on base claim 1 (App. Br.
20). As discussed above with respect to claim 9, Appellants have not shown
that the Examiner erred in finding that the combination of Talbot in view of
Official Notice and Nova teaches or would have suggested the limitations of
claim 9. Accordingly, we conclude that Appellants have also not shown that
the Examiner erred in rejecting claims 11-13 over the combination of Talbot,
Official Notice, and Nova in view of Okin under 35 U.S.C. § 103(a).
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VI. CONCLUSIONS
(1) Appellants have not shown that the Examiner erred in finding
that claims 1, 3, 5, 7, and 8 are anticipated by the teachings of Reeves.
(2) Appellants have not shown that the Examiner erred in finding
that claims 2 and 6 are unpatentable over the teachings of Reeves in view of
Talbot.
(3) Appellants have not shown that the Examiner erred in finding
that claim 4 is unpatentable over the teachings of Reeves in view of Official
Notice.
(4) Appellants have not shown that the Examiner erred in finding
that claims 9-10 and 14-22 are unpatentable over the teachings of Talbot in
view of Official Notice and Nova.
(5) Appellants have not shown that the Examiner erred in finding
that claims 11-13 are unpatentable over the teachings of Talbot, Official
Notice, and Nova in view of Okin.

VII. DECISION
The Examiner’s decision rejecting claims 1-22 under 35 U.S.C. §
102(b) and § 103(a) is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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