11541354 (B.P.A.I. Aug. 18, 2011)

Ex Parte Shepard

Board of Patent Appeals and InterferencesAug 18, 2011

11541354 (B.P.A.I. Aug. 18, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/541,354 09/29/2006 Daniel Robert Shepard NUP-005C1/7301813001 1712 23517 7590 08/19/2011 BINGHAM MCCUTCHEN LLP 2020 K Street, N.W. Intellectual Property Department WASHINGTON, DC 20006 EXAMINER LE, DIEU MINH T ART UNIT PAPER NUMBER 2114 MAIL DATE DELIVERY MODE 08/19/2011 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________________ Ex parte DANIEL ROBERT SHEPARD ____________________ Appeal 2009-012078 Application 11/541,354 Technology Center 2100 ____________________ Before KALYAN K. DESHPANDE, DAVID M. KOHUT, and JASON V. MORGAN, Administrative Patent Judges. DESHPANDE, Administrative Patent Judge. DECISION ON APPEAL Appeal 2009-012078 Application 11/541,354 2 STATEMENT OF CASE1 The Appellant seeks review under 35 U.S.C. § 134 of a rejection of claims 10-21, the only claims pending in the application on appeal. We have jurisdiction over the appeal pursuant to 35 U.S.C. § 6(b). We REVERSE and ENTER A NEW GROUND OF REJECTION PURSUANT TO 37 C.F.R §41.50(b). The Appellant invented semiconductor memory devices in which the addressing pattern is optimized to better facilitate error correcting techniques and reduce device testing. Specification 1. An understanding of the invention can be derived from a reading of exemplary claim 10, which is reproduced below [bracketed matter and some paragraphing added]: 10. An array of bits comprising: [1] a first plurality of lines of bits; and [2] a second plurality of lines of bits intersecting the first plurality of lines, [3] wherein the first plurality of lines and the second plurality of lines form a two-dimensional array, and accessing the bits in the array is performed by alternating between accessing different lines in the first plurality of lines and accessing different lines in the second plurality of lines. REFERENCES The Examiner relies on the following prior art: Stenfort US 6,457,156 B1 Sep. 24, 2002 1 Our decision will make reference to the Appellant’s Appeal Brief (“App. Br.,” filed May 5, 2008) and Reply Brief (“Reply Br.,” filed Aug. 26, 2008), and the Examiner’s Answer (“Ans.,” mailed Jul. 7, 2008), and Final Rejection (“Final Rej.,” mailed Oct. 9, 2007). Appeal 2009-012078 Application 11/541,354 3 REJECTIONS2 Claims 10-21 stand rejected under 35 U.S.C § 102(e) as being anticipated by Stenfort. Ans. 3. ISSUE The issue of whether the Examiner erred in rejecting claims 10-21 under 35 U.S.C. § 102(e) as anticipated by Stenfort turns on whether Stenfort describes an array of bits accessed by alternating between accessing different lines. FACTS PERTINENT TO THE ISSUES The following enumerated Findings of Fact (FF) are supported by a preponderance of the evidence. Facts Related to the Prior Art Stenfort 01. Stenfort is directed to methods for correcting errors in data that is read from a physical medium. Stenfort 1:6-8. 02. Stenfort describes a method that includes (a) reading a data frame and associated check bytes from a media, (b) generating an error correction model for the data frame and associated check 2 We have decided the appeal before us. However, should there be further prosecution of these claims, the Examiner’s attention is directed to the recently issued guidance from the Director, Subject Matter Eligibility of Computer Readable Media, 1351 Off. Gaz. Pat. Office 212 (Feb. 23, 2010); and In re Nuijten, 500 F.3d 1346 (Fed. Cir. 2007). Appeal 2009-012078 Application 11/541,354 4 bytes, where the error correction model is defined by non-zero syndromes in the check bytes of Q dimension code words and P dimension code words of the data frame, (c) examining the generated error correction model, and (d) correcting the data frame using a combination of error correction systems that are selected based on the examining of the generated error correction model. Stenfort 2:59-67. 03. During operation, correction for a particular dimension is performed on all code words that lie along one dimension, and then correction will be performed along the other dimension, over all of those code words. Stenfort 7:48-54. ANALYSIS Claims 10-21 rejected under 35 U.S.C §102(e) as being anticipated by Stenfort The Appellant contends that Stenfort fails to describe an array of bits accessed by alternating between accessing different lines, as required by claim 14 and as recited in claim 10. App. Br. 5-6 and Reply Br. 4-5. We agree with the Appellant. Claims 10 and 14 require a plurality of lines of bits wherein accessing the bits is performed by alternating between accessing different lines within the plurality of lines. Stenfort describes a method for correcting errors in data. FF 01. The method includes generating an error correction model for the data frame and associated check bytes, where the error correction model is defined by non-zero syndromes in the check bytes of Q dimension code words and P dimension code words of the data frame. FF 02. Appeal 2009-012078 Application 11/541,354 5 However, Stenfort explicitly describes that correction is performed on all code words that lie along one dimension and then along the other dimension. FF 03. That is, the correction is performed on a first line in its entirety before performing the correction on a second line. We agree with Appellant that the claimed “alternating” limitation, given the broadest reasonable construction in light of the Specification, requires an access pattern involving multiple lines of bits in an alternating manner. Reply Br. 4-6, Specification 5-6, and Fig.2). Stenfort describes that code words are corrected in one dimension without accessing bits in another dimension and as such Stenfort does not describe alternating between accessing different lines. The Examiner further points to a description in Stenfort that uses the term “alternatively.” Ans. 9. However, we agree with the Appellant that this term is used to illustrate an alternative embodiment and not alternating between accessing different lines. The Appellant further contends that Stenfort fails to describe an array of bits accessed by simultaneously accessing different lines, as required by claim 19. App. Br. 8 and Reply Br. 7. We agree with the Appellant. Claims 19 require a plurality of lines of bits wherein accessing the bits is performed by simultaneously accessing different lines within the plurality of lines. As discussed supra, Stenfort explicitly describes that correction is performed on all code words that lie along one dimension and then along the other dimension. FF 03. We have found no evidence that Stenfort ever performs such corrections simultaneously in both dimensions. Instead, the correction is performed on a first line in its entirety before performing the Appeal 2009-012078 Application 11/541,354 6 correction on a second line. As such, Stenfort does not describe simultaneously accessing different lines. As such, we find that Stenfort fails to anticipate claims 10-21. NEW GROUND OF REJECTION The following new ground of rejection is entered pursuant to 37 C.F.R. § 41.50(b). Independent claims 10, 14, and 19 are rejected under 35 U.S.C. § 101 as being directed towards non-statutory subject matter. Under 35 U.S.C. § 101, four categories of subject matter are eligible for patent protection: (1) processes; (2) machines; (3) manufactures; and (4) compositions of matter. Patentable subject matter must fall within one of the categories set out in 35 U.S.C. § 101 - “Those four categories define the explicit scope and reach of subject matter patentable under 35 U.S.C. § 101 ….” In re Nuijten, 500 F.3d 1346, 1357 (Fed. Cir. 2007), reh'g denied en banc, 515 F.3d 1361 (Fed. Cir. 2008), and cert. denied, 129 S. Ct. 70 (2008)). Software itself, with no structural tie to an article of manufacture, machine, process or composition of matter, is not patentable subject matter. See Nuijten, 500 F.3d at 1357. Here, claims 10, 14, and 19 recite “an array of bits.” An array of bits is nothing more than an abstract idea. Claims 10, 14, and 19 fail to recite any structural tie between the recited “array of bits” and any of the four categories of patent eligible subject matter. The requirements of claims 10, 14, and 19 can be accomplished by human activity alone, including through mental processes only. As such, these claims are directed to an abstract idea. Appeal 2009-012078 Application 11/541,354 7 Furthermore, the Supreme Court has held that certain categories of subject matter are not entitled to patent protection. Gottschalk v. Benson, 409 U.S. 63, 67 (1972). The Supreme Court explained that there are three categories of subject matter for which one may not obtain patent protection. These judicially-created exceptions are “laws of nature, natural phenomena, and abstract ideas.” Diamond v. Diehr, 450 U.S. 175, 185 (1981). The Supreme Court has recently stated that the machine or transformation test is “a useful and important clue” as to whether inventions are processes under § 101 but has cautioned that it is not the sole test for deciding patent eligibility. Bilski v Kappos, 130 S.Ct. 3218, 3221 (2010). The elements of claims 10, 14, and 19 do not require the use of any machine. These claims only recite “bits” which neither explicitly nor implicitly require the use of a machine. Furthermore, the recited “bits” are not transformed in any manner by claims 10, 14, and 19. As such, claims 10, 14, and 19 fail the machine-or-transformation test and as discussed supra, are directed towards an abstract idea. CONCLUSIONS OF LAW The Examiner erred in rejecting claims 10-21 under 35 U.S.C. § 102(e) as anticipated by Stenfort. A new ground of rejection is entered 37 C.F.R. § 41.50(b) and claims 10, 14, and 19 are rejected under 35 U.S.C. § 101 as being directed towards non- statutory subject matter. Appeal 2009-012078 Application 11/541,354 8 DECISION To summarize, our decision is as follows.  The rejections of claims 10-21 under 35 U.S.C. § 102(e) as anticipated by Stenfort is not sustained.  A new ground of rejection is entered pursuant to 37 C.F.R. § 41.50(b). o Claims 10, 14, and 19 are rejected under 35 U.S.C. § 101 as being directed towards non-statutory subject matter. This decision contains new grounds of rejection pursuant to 37 CFR § 41.50(b). 37 CFR § 41.50(b) provides “[a] new ground of rejection pursuant to this paragraph shall not be considered final for judicial review.” 37 CFR § 41.50 (b) also provides that the appellant, WITHIN TWO MONTHS FROM THE DATE OF THE DECISION, must exercise one of the following two options with respect to the new ground of rejection to avoid termination of the appeal as to the rejected claims: (1) Reopen prosecution. Submit an appropriate amendment of the claims so rejected or new evidence relating to the claims so rejected, or both, and have the matter reconsidered by the examiner, in which event the proceeding will be remanded to the examiner …. (2) Request rehearing. Request that the proceeding be reheard under § 41.52 by the Board upon the same record …. Appeal 2009-012078 Application 11/541,354 9 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv)(2010). REVERSED 37 C.F.R. § 41.50(b) msc