Ex Parte Sheffield et al

Patent Trial and Appeal Board

Aug 30, 2016

13405846 (P.T.A.B. Aug. 30, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/405,846 02/27/2012
31292 7590 09/01/2016
CHRISTOPHER & WEISBERG, PA
200 EAST LAS OLAS BOULEVARD
SUITE 2040
FORT LAUDERDALE, FL 33301
FIRST NAMED INVENTOR
Robert Sheffield
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
22493-246CON
(15901ROUS02
9806
EXAMINER
RUFO, LOUIS J
ART UNIT PAPER NUMBER
1759
NOTIFICATION DATE DELIVERY MODE
09/01/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ptomail@cwiplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ROBERT SHEFFIELD and EILEEN GOULET 1
Appeal2015-003224
Application 13/405,846
Technology Center 1700
Before BRADLEY R. GARRIS, ADRIENE LEPIANE HANLON, and
JEFFREY R. SNAY, Administrative Patent Judges.
GARRIS, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134 from the Examiner's
decision rejecting claims 19-29 and 34--38. We have jurisdiction under
35 U.S.C. § 6.
We AFFIRM.
1 Rockstar Consortium US LP is identified as the real party in interest. App.
Br. 1.
Appeal2015-003224
Application 13/405,846
Appellants claim a method of manufacturing a circuit board having a
conductive trace comprising the step of reducing a surface roughness of a
conductive trace surface by vacuum depositing conductive material on the
surface (independent claim 19) or the steps of reducing a surface roughness
and applying an adhesion promoter to the surface (independent claim 34).
A copy of representative claims 19 and 34, taken from the Claims
Appendix of the Appeal Brief, appears below.
19. A method of manufacturing a circuit board, the method
compnsmg:
providing a first circuit board layer, the first circuit board layer having
a surface and a conductive circuit trace on the surface of the first circuit
board layer, the conductive trace having at least one surface;
reducing a surface roughness of the at least one surface of the
conductive circuit trace by vacuum depositing conductive material on the at
least one surface; and
laminating the first circuit board layer with a second circuit board
layer.
34. A method of manufacturing a circuit board, the method
compnsmg:
providing a first circuit board layer of a circuit board, the first circuit
board layer having a surface and a conductive circuit trace on the surface of
the first circuit board layer, the conductive trace having at least one surface;
reducing a surface roughness of the at least one surface of the
conductive circuit trace;
applying an adhesion promoter to the at least one surface of the
conductive circuit trace; and
laminating the first circuit board layer with a second circuit board
layer.
Under 35 U.S.C. § 103(a), the Examiner rejects as unpatentable:
claims 19-21, 25-27, 29, 34--36, and 38 over Daigle et al. (US
5,046,238, issued Sept. 10, 1991) ("Daigle") in view ofFushie et al. (US
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Application 13/405,846
2002/0100608 Al, published Aug. 1, 2002) ("Fushie") or over Tanaka et al.
(US 4,959,507, issued Sept. 25, 1990) ("Tanaka") in view of Fushie and
Daigle as evidenced by Liu et al. (US 6,037,258, issued Mar. 14, 2000)
("Liu"); and
remaining dependent claims 22-24, 28, and 37 over these respective
sets of references in combination with additional prior art.
Appellants present arguments specifically directed to independent
claims 19 and 34 as well as dependent claims 20, 21, and 29 (App. Br. 6-
13). Remaining dependent claims 22-28 and 35-38 will stand or fall with
their parent independent claims (id. at 2).
We sustain the above rejections for the reasons expressed in the Final
Action, the Answer, and below.
In rejecting the independent claims over Daigle and Fushie, the
Examiner concludes that it would have been obvious to provide the
conductive traces of Daigle with the sputtered (i.e., vacuum deposited)
copper/adhesion-promoter layers taught by Fushie to enhance adhesion
(Final Action 6-9). The Examiner determines that such sputtering/vacuum
depositing is indistinguishable from the claimed vacuum depositing and
therefore would be expected to inherently reduce surface roughness of
Daigle's traces (id. at sentences bridging 6-7 and 8-9; Ans. i-f bridging 15-
16).
In this latter regard, Appellants state that "Fushie does not disclose
reducing a surface roughness of a conductive trace" (App. Br. 7) but do not
contest or otherwise address the Examiner's determination that Fushie' s
sputtering of conductive material inherently would reduce surface roughness
of Daigle' s trace.
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Appeal2015-003224
Application 13/405,846
Appellants argue that Fushie' s copper film 6 is covered by a resin
protective layer 8 rather than a sputtered conductive material (id.) and that
copper film 6 is a conductive layer that extends over the expanse of the
printed circuit board rather than a conductive trace (id. at 8).
For the reasons given by the Examiner, Fushie discloses sputtering
conductive material on copper film 6 (see, e.g., Ans. 14). In advocating their
opposing view, Appellants refer to "Fushie, i-f [0034], which clearly
describes 'a resin 8 serving as a protective layer covering the copper film 6"'
(Reply Br. 3--4) and argue "[h]ence, Fushie does not describe depositing a
conductive material on a conductive circuit trace" (id. at 4). We emphasize,
however, that Appellants' quotation of Fushie's i-f 34 disclosure is
incomplete by omitting the teaching that resin 8 is "covering the copper film
6 inside the through hole 3" (i-f 34 (underlining added)). Appellants do not
identify any disclosure in Fushie that resin 8 covers copper film 6 in the
planar areas of the circuit board which are outside through hole 3. In
addition, we agree with the Examiner (i) that, contrary to Appellants' above
argument, copper film 6 does not extend over the expanse of Fushie' s circuit
board because it is broken up by insulating layer 10 as shown in Figure 6,
(ii) that accordingly it is appropriate to consider this copper film as a
conductive trace, and (iii) that in any event Daigle rather than Fushie is
relied on for the disclosure of conductive traces (Ans. 17).
In rejecting the independent claims over Tanaka, Fushie, and Daigle
as evidenced by Liu, the Examiner concludes that it would have been
obvious to modify Tanaka so that first and second circuit board layers are
laminated together as taught by Daigle and so that the conductive traces are
provided with a sputtered (i.e., vacuum deposited) copper/adhesion-
promoter as taught by Fushie whereby the surface roughness of the traces
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Appeal2015-003224
Application 13/405,846
would be reduced as desired by Tanaka as evidenced by Liu's disclosure of a
vacuum deposition technique for reducing surface roughness (Final Action
10-11 and 13).
Appellants argue that reducing surface roughness of a conductive
trace by vacuum depositing conductive material is not disclosed by Tanaka,
Fushie, or Daigle (App. Br. 9) and that "Liu fails to cure the deficiencies of
Tanaka, Fushie, and Daigle" (id. at 10). According to Appellants, "the
smooth surface obtained by Liu is obtained by an Argon purge between
vacuum deposition processes that deposit a conductive layer on a board"
(id.), and "[b ]y introducing an Argon purge - which is not a deposition - to
smooth the surface, Liu teaches away from relying on a vapor deposition
alone to achieve smoothness" (id.).
We fully agree with the Examiner's finding that Liu discloses forming
a smooth surface layer by a vacuum deposition technique that includes
sequentially depositing half layers with an intermediate argon purge in order
to limit surface temperature and thereby prevent formation of an undesirable
rough top surface topography (Ans. 17-18 (citing Liu col. 4, 11. 31---65)).
Contrary to Appellants' apparent belief, Liu expressly teaches that the steps
of vacuum depositing half layers participate in limiting surface temperature
and thereby surface roughness (see, e.g., Liu col. 4, 11. 31--45). As indicated
above, Appellants contend that "[b ]y introducing an Argon purge - which is
not a deposition - to smooth the surface, Liu teaches away from relying on a
vapor deposition alone to achieve smoothness" (App. Br. 10 (underlining
added)). However, Appellants do not identify any language of the
independent claims that excludes a vacuum depositing technique comprising
sequential depositing steps with an intermediate argon purge as taught by
Liu.
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Appeal2015-003224
Application 13/405,846
Regarding dependent claims 20 and 21, Appellants contend "[t]he
cited references do not disclose the more precise deposition recited in
Applicants' claims which can be directed laterally, along the direction of the
conductive trace, or transversely, across the conductive trace" (App. Br. 11 ).
We share the Examiner's position that, in the prior art combinations
discussed above, "deposition is provided in all directions" (Ans. 18) thereby
resulting in roughness reduction in all directions including directions along
as well as across the circuit trace as claimed. As clarification, we point out
that claims 20 and 21 are not limited to roughness reductions only in the
recited directions.
Finally, Appellants present the following argument regarding
dependent claim 29.
Claim 29 recites "reducing a roughness of at least one
side surface of the circuit board trace." In its rejection of this
claim, the Office Action asserts that the cited references to
Tanaka, Fushie and Daigle "further disclose where the
roughness of at least one surface of the circuit board trace is
reduced, namely the upper surface." Even if these references
showed reduction of roughness of the upper surface, they do not
show reduction of roughness to a side surface of the circuit
board trace by vacuum deposition. For at least these additional
reasons, Claim 29 is allowable, and its rejection should be
reversed.
App. Br. 11-12.
In response, the Examiner determines that the broadest reasonable
interpretation of the claim 29 recitation "one side" surface includes a surface
on the upper side of the conductive trace (Ans. 18).
Appellants argue that the Examiner's interpretation is inconsistent
with their Specification because "Applicants' [S]pecification at page 9
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Application 13/405,846
clearly distinguishes between the side surface of [the] conductive trace and
the upper and lower surfaces of the conductive trace" (Reply Br. 5).
While page 9 of the Specification refers to upper surfaces, bottom
surfaces, and side surfaces (not illustrated) of a conductive trace, Appellants
do not specifically identify the disclosure on page 9 that they believe
requires interpreting the phrase "one side" of claim 29 to exclude the upper
side of a conductive trace. For example, Appellants do not identify any
disclosure of a definition for the term "side" that would exclude an upper
side of a trace. On the other hand, the term "side" is commonly defined as
broadly including a surface of an object (see, e.g., WEBSTER'S II New
Riverside University Dictionary 1984) without regard to whether it is an
upper, lower, or lateral surface. Under these circumstances, Appellants do
not show error in the Examiner's interpretation of claim 29.
For the reasons stated above and given by the Examiner, Appellants'
arguments fail to reveal error in the Examiner's rejections of independent
claims 19 and 34 and dependent claims 20, 21, and 29.
The decision of the Examiner is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l).
AFFIRMED
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