11346718 (B.P.A.I. Jun. 30, 2009)

Ex Parte Shastri et al

Board of Patent Appeals and InterferencesJun 30, 2009

11346718 (B.P.A.I. Jun. 30, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Ex parte KALPENDU SHASTRI, VIPULKUMAR PATEL, DAVID PIEDE, and JOHN FANGMAN ____________ Appeal 2008-005375 Application 11/346,718 Technology Center 2800 ____________ Decided:1 June 30, 2009 ____________ Before CHUNG K. PAK, TERRY J. OWENS, and CATHERINE Q. TIMM Administrative Patent Judges. TIMM, Administrative Patent Judge. DECISION ON REQUEST FOR REHEARING 1 The two-month time period for filing an appeal or commencing a civil action, as recited in 37 C.F.R. § 1.304, begins to run from the Decided Date shown on this page of the decision. The time period does not run from the Mail Date (paper delivery) or Notification Date (electronic delivery). Appeal 2008-005375 Application 11/346,718 2 On March 11, 2009, Appellants filed a Request for Rehearing of the Decision of January 13, 2009. In that Decision, the panel affirmed the Examiner’s decision to reject claims 1 and 5 under 35 U.S.C. § 102(b) as anticipated by U.S. Application Publication No. 2002/0172464 A1, published November 21, 2002 in the name of Delwala (hereinafter “Delwala”). The panel also reversed the Examiner’s decision to reject claims 1 and 4 under 35 U.S.C. § 102(b) as anticipated by U.S. Application Publication No. 2003/0113067 A1, issued June 19, 2003 to Koh et al., and the panel entered a new ground of rejection for claims 4 and 5 under 35 U.S.C. § 112, first paragraph, as lacking written description support in Appellants’ Specification. In their Request, Appellants contend that we misapprehended the teachings of Delwala.2 Specifically, Appellants contend that, in our Factual Finding 16 (FF 16), we incorrectly found that Figure 52 of Delwala shows electronic circuit 5101 as part of the flip chip portion 5902. According to Appellants, “the electronic circuit 5101 is always formed as part of the ‘SOI- based integrated circuit’ within flip chip portion 5904” (Request 2). In support of this contention, Appellants reproduce Figure 52 in an attachment and assert that “the circular cut-out (labeled ‘C’ in the attachment) is intended to show an opening through chip portion 5902, to show the location of electronic circuit 5101 in the final assembly” (Request 2). Further, Appellants quote paragraphs 234, 253, and 259 of Delwala to further support 2 While Appellants refer to the reference as “Deliwala,” the first named inventor for U.S. Published Application No. 2002/0172464 A1 is “Delwala.” Appeal 2008-005375 Application 11/346,718 3 the assertion that electronic circuit 5101 cannot be considered part of flip chip portion 5902. Appellants’ request raises the following issue: have the Appellants shown that the panel reversibly erred in finding that Figure 52 shows electronic circuit 5101 formed in flip chip portion 5902 rather than in flip chip portion 5904? Figure 52 from the attachment to Appellants’ Request is reproduced below. Appeal 2008-005375 Application 11/346,718 4 Figure 52 depicts the partially exploded perspective view of an alternative embodiment of the integrated optical/electronic circuit using flip chips, with a portion marked by Appellants as area “C” (Delwala, ¶ 77; Request 2). As explained below, Appellants have not persuaded us of any reversible error in our Decision. In particular, Appellants have not persuaded us that we reversibly erred in finding that Figure 52 shows electronic circuit 5101 formed in flip chip portion 5902. As a first matter, we disagree with the Appellants’ characterization of the area they have labeled “C” in their reproduction of Figure 52 as constituting a “cut out . . . intended to show an opening through chip portion 5902” (Request 2). Appellants provide no citation to any portion of Delwala to support such a contention, and we find no such suggestion in the disclosure of Delwala. Delwala states “[b]oth of the embodiments of optical electronic I/O flip portion 5902 as shown in FIGS. 53 and 54 include the electronic device 5101, as described relative to FIG. 43”3 (Delwala, ¶ 259). Further, Delwala appears to teach that the area Appellants designate “C” is not a cut-out, but a “radius” or boundary area. Delwala states: To provide a circuit layout for the integrated optical/electronic circuit 103, a radius can initially be drawn around the active optical waveguide devices 150, the passive optical waveguide devices 800, and the light coupling portion 5110 to 3 Although paragraph 259 refers to Figures 53 and 54, Delwala teaches that “FIGS. 53 and 54, respectively, illustrate two embodiments of integrated optical circuit 103 using flip-chip technology that is similar to the embodiment of integrated optical/electronic circuit 103 illustrated respectively in FIGS. 51 and 52, except that the electronic device 5101 is not included in the FIGS. 53 and 54 embodiments” (Delwala, ¶ 268). Appeal 2008-005375 Application 11/346,718 5 indicate where the electronic devices 5101 are not to be located. The electronic devices 5101 can be located everywhere else on the optical/electronic flip chip portion 5902 that does not conflict with the light coupling portion 5110. (Delwala, ¶ 267 (emphasis added).) That one of ordinary skill reading Delwala would understand electronic device 5101 to be located on flip chip portion 5902 is further supported by the inclusion of solder balls 5930 on the top surface of electronic device 5101. We note that Delwala states: The uppermost layer of the electronic device 5101 is in electrical communication with solder balls 5930. The solder balls 5930 are used, when inverted, to solder the integrated optical/electronic circuit 103 to, e.g., a motherboard or some other printed circuit board to which the integrated optical/electronic circuit 103 is being operationally secured. The solder balls 5930 also provide the electrical connection between the electrical circuits on the printed circuit board and the electrical circuits in the electronic device 5101 of the integrated optical/electric circuit 103. (Delwala, ¶ 266). If solder balls 5930 are on an uppermost layer of electronic device 5101 and must be accessible to a motherboard or printed circuit board to provide electrical connections thereto, electronic device 5101 must be positioned in Figure 52 on an exterior surface of flip chip portion 5902, such as over light coupling portion 5110. Accordingly, Delwala supports the panel’s finding in its Decision that electronic devices 5101 are located as part of flip chip portion 5902 and separate from the SOI-based integrated circuit portion 5904. We cannot Appeal 2008-005375 Application 11/346,718 6 agree with Appellants’ contention that the panel reversibly erred in this regard. The subject Request has been granted to the extent that the Decision has been reconsidered, but is denied with respect to making any changes therein. DENIED cam WENDY W. KOBA, ESQ. P O BOX 556 SPRINGTOWN PA 18081