Ex parte Seelbach

Board of Patent Appeals and Interferences

Jul 7, 1999

08650023 (B.P.A.I. Jul. 7, 1999)

Application for patent filed May 17, 1996. According to1
appellant, this application is a continuation of Application
08/301,093, filed September 6, 1994, now abandoned.
1
THIS OPINION WAS NOT WRITTEN FOR PUBLICATION
The opinion in support of the decision being entered today
(1) was not written for publication in a law journal and
(2) is not binding precedent of the Board.
Paper No. 22
UNITED STATES PATENT AND TRADEMARK OFFICE
__________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
__________
Ex parte WALTER C. SEELBACH
__________
Appeal No. 97-3082
Application 08/650,0231
__________
ON BRIEF
__________
Before HAIRSTON, KRASS, and MARTIN, Administrative Patent
Judges.
KRASS, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal from the final rejection of
claims 1 and 4. Claims 6 through 8 have been allowed and
Appeal No. 97-3082
Application No. 08/650,023
2
claims 2, 3 and 5 have been cancelled.
The invention is directed to providing a bandgap voltage
in low voltage submicron CMOS technology so as to provide a
bandgap reference voltage that will operate at reduced power
supply voltages and can be referenced to a power supply
terminal.
Independent apparatus claim 1 is reproduced as follows:
1. A CMOS circuit for providing a current having a
positive temperature coefficient, the circuit comprising:
CMOS parasitic P-N junction means for generating a delta
voltage having a positive temperature coefficient;
CMOS differential amplifying means responsive to said
delta voltage for providing differential currents; and
summing means responsive to said differential currents
for providing a resulting current at an output of said summing
means, said current having a positive temperature coefficient,
and a feedback connection absent between said output of said
summing means and said CMOS parasitic P-N junction means.
The examiner relies on the following reference:
Cave et al. (Cave) 5,087,830 Feb. 11,
1992
Claims 1 and 4 stand rejected under 35 U.S.C. § 112,
second paragraph, as being vague and indefinite for relying on
a negative limitation, “a feedback connection absent” or
“without using feedback.” Claims 1 and 4 stand further
Appeal No. 97-3082
Application No. 08/650,023
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rejected under 35 U.S.C. § 102(b) as anticipated by Cave.
Reference is made to the brief and answer for the
respective positions of appellant and the examiner.
OPINION
We reverse.
Turning first to the rejection under 35 U.S.C. § 112,
second paragraph, the examiner contends that the claim
language regarding “feedback” is a “negative limitation” and,
therefore, indefinite. At page 4 of the answer, the examiner
contends that there “must be support in the specification for
the language recited in the claims” and that nowhere “is there
anything disclosed in the specification that would set forth
this limitation.” The examiner deems claims 1 and 4 “to be
inconsistent with the description in the specification.”
As both appellant and the examiner understand, a
“negative limitation” in a claim, does not, per se, make the
claim indefinite under 35 U.S.C. § 112, second paragraph. The
examiner’s complaint about a lack of “support” in the
specification sounds more like a problem under the written
description section of the first paragraph of 35 U.S.C. § 112,
Appeal No. 97-3082
Application No. 08/650,023
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but the examiner has not made such a rejection. However, it
appears to us, from a review of the drawing itself, that there
is no feedback connection between the output of the summing
means, node 46, and the CMOS parasitic P-N junction means,
transistors 28-31. Thus, the drawing, which is part of the
disclosure, is consistent with what is claimed and we find
nothing indefinite about the cited claim language.
Accordingly, we will not sustain the rejection of claims 1 and
4 under 35 U.S.C. § 112, second paragraph.
We now turn to the rejection of the claims under 35
U.S.C.
§ 102(b) as anticipated by Cave. Appellant makes one argument
in this regard and that is that Cave fails to disclose the
claimed “feedback connection absent between said output of
said summing means and said CMOS parasitic P-N junction
means.” Indeed, Cave discloses that there is such a feedback
connection (e.g., see Cave’s abstract).
The examiner does not deny that the feedback path exists
in Cave, directly contrary to the instant claim language, but
argues only that “it is not understood what is meant by the
recitation concerning the ‘feedback connection’ or how such a
Appeal No. 97-3082
Application No. 08/650,023
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‘feedback connection’ is connected in the circuit” [answer-
page 5]. If the claim language is so indefinite that the
examiner cannot understand the claimed subject matter, then it
appears that a prior art rejection should not have been made
since it would be impossible to apply the teachings of the
prior art to the claim language. If a prior art rejection is
to be made to the extent the claimed subject matter is
understood, then the examiner may not choose to ignore any
limitations appearing in the claims. However, it is clear
from the examiner’s response to appellant’s arguments that the
examiner did, indeed, read out the “feedback connection
absent...” and “without using feedback...” limitations from
the claims in applying the reference to the claimed subject
matter. Therefore, we will not sustain the rejection of
claims 1 and 4 under 35 U.S.C. § 102(b).
We also find it strange that the examiner questions where
“the ‘feedback connection’ is provided” in the circuit
[answer-top of page 5] and “how such a ‘feedback connection’
is connected in the circuit” [answer-bottom of page 5]. The
claims clearly call for there to be no feedback connection so
how can the examiner question where and how such a connection
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is provided in the circuit? The simple answer is that it is
not so provided.
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Application No. 08/650,023
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The examiner’s decision is reversed.
REVERSED
Kenneth W. Hairston )
Administrative Patent Judge )
)
)
)
Errol A. Krass ) BOARD OF
PATENT
Administrative Patent Judge ) APPEALS AND
) INTERFERENCES
)
)
John C. Martin )
Administrative Patent Judge )
tdc
Appeal No. 97-3082
Application No. 08/650,023
8
Vincent B. Ingrassia
Motorola Inc.
Intellectual Property Dept.
P.O. Box 10219
Scottsdale, AZ 85271-0219