Ex Parte Seaman et al

Patent Trial and Appeal Board

Sep 20, 2013

10921225 (P.T.A.B. Sep. 20, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD

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Ex parte KEVIN L. SEAMAN and VERNON M. WNEK
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Appeal 2011-011910
Application 10/921,225
Technology Center 3700
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Before: JENNIFER D. BAHR, GAY ANN SPAHN, and
MICHELLE R. OSINSKI, Administrative Patent Judges.

BAHR, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF THE CASE
Kevin L. Seaman and Vernon M. Wnek (Appellants) appeal under
35 U.S.C. § 134 from the Examiner’s decision rejecting claims 15, 19, and
21-24 under 35 U.S.C. § 103(a) as being unpatentable over Horiuchi (US
6,229,099 B1, iss. May 8, 2001). We have jurisdiction under 35 U.S.C.
§ 6(b).
We REVERSE.
The Claimed Subject Matter
Claim 15, reproduced below, is illustrative of the claimed subject
matter.
15. A method for designing a land pattern for mating an
integrated circuit device to a printed circuit board, the method
comprising the steps of:
determining a number of required pads;
selecting a land pattern to yield the required pads;
determining a number of required perimeter routing
channels; and
optimizing a size of the land pattern to yield the required
perimeter routing channels, said optimizing step including
under populating at least one perimeter edge of the land pattern
on the surface of the printed circuit board to form a first non-
fully populated perimeter edge of pads,
wherein the first non-fully populated perimeter edge of
pads includes a number of spaces that each represent space for a
single pad;
wherein a ratio of pads in the first non-fully populated
perimeter edge of pads to the number of spaces is at least two to
one (2:1).

OPINION
Independent claim 15 requires the optimizing step to include “under
populating at least one perimeter edge of the land pattern on the surface of
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the printed circuit board to form a first non-fully populated perimeter edge
of pads, wherein the first non-fully populated perimeter edge of pads
includes a number of spaces that each represent space for a single pad” and
“a ratio of pads in the first non-fully populated perimeter edge of pads to the
number of spaces is at least two to one (2:1).”
The Examiner relies on the land patterns depicted in figures 1, 13, and
20 of Horiuchi for disclosure of under populating at least one perimeter edge
as called for in claim 15. Ans. 3-4.
Appellants argue that Horiuchi does not teach or suggest that the
pattern of figure 1 is disposed on the surface of a circuit board. App. Br. 9.
We agree with Appellants. Horiuchi’s figure 1 “is a view illustrating circuit
patterns arranged between the lands in an enlarged scale” (col. 5, ll. 36-37),
and is used as a visual reference to facilitate the introduction and definitions
of the various parameters (“a,” “b,”, “c,” and “d”) (col. 3, ll. 1-16). Horiuchi
gives no indication that the patterns depicted in figure 1 are associated with
any particular layer of the board and does not specify whether figure 1
depicts a perimeter edge of the board. Thus, Horiuchi’s figure 1 does not
describe the under populating limitations of claim 15.
Appellants argue that the Examiner’s reliance on figure 13 is
misplaced, because Horiuchi’s figure 13 illustrates a pattern on a second
layer of the circuit board, not on the surface of the circuit board, as required
in claim 15. App. Br. 9. Appellants are correct. See Horiuchi, col. 9, ll. 58-
60. Figure 12, which illustrates the pattern on the first layer,1 shows fully
populated perimeter edges. Horiuchi, col. 9, ll. 46-47.

1 Horiuchi refers to the layer on which the semiconductor chip is joined as
the “first layer.” Col. 7, ll. 9-10.
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The Examiner responds that:
[Horiuchi] et al teach a multilayer board which can have two or
more circuit pattern layers combined to form the printed circuit
board (PCB) and Fig. 12 can be one surface layer while only
Fig. 13 is another surface layer needed to be coupled together
with Fig. 12 to form the PCB. Therefore, one of skill in the art,
with respect to [Horiuchi] et al’s teaching, at a minimum can
obtain a two-layer PCB with the circuit pattern of Fig. 13 on the
surface of the PCB, as claimed.
Ans. 5-6.
The Examiner’s response does not cogently explain how Horiuchi’s
disclosure of a circuit pattern which is not on the surface is pertinent to the
land pattern on the surface of the printed circuit board called for in claim 15.
While Horiuchi does disclose a multi-layer board, of which two of the layers
may have patterns as depicted in figures 12 and 13, Horiuchi does not
disclose use of the pattern of figure 13 on the surface of the board. While
the Examiner’s position is not entirely clear, the Examiner appears to be
reasoning that a person of ordinary skill in the art could design a two-layer
printed circuit board with the circuit pattern of figure 13 on the surface, but
does not articulate any reason why it might have been obvious to do so,
especially in light of Horiuchi’s illustrative examples, which all have fully
populated surface (i.e., first) layers. See figs. 2, 12, 20.
Figure 20 depicts a staggered lattice form (col. 6, ll. 35-41), with all of
the land positions in the perimeter edges of that staggered lattice form being
populated. Thus, Horiuchi’s figure 20 pattern also fails to describe the under
populating limitations of claim 15.
The Examiner also alludes to column 3, lines 28-30 of Horiuchi with
regard to under populating. Ans. 3. However, that passage merely points
out that there are n-2 intermediate lands extending between the end lands in
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a row or column with n lands, and that a circuit pattern can be drawn from
each of these lands. The passage does not describe under populating as
called for in claim 15.
For the above reasons, we do not sustain the rejection of claim 15 and
of its dependent claims 19 and 21-24 as unpatentable over Horiuchi.

DECISION
The Examiner’s decision rejecting claims 15, 19, and 21-24 is
reversed.

REVERSED

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