Ex Parte Seabaugh et al

Patent Trial and Appeal Board

Aug 14, 2017

14212310 (P.T.A.B. Aug. 14, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/212,310 03/14/2014 Alan Seabaugh 135404.UND13007US2-P1407 9948
34018 7590 08/16/2017
Greenberg Traurig, LLP
77 W. Wacker Drive
Suite 3100
CHICAGO, IL 60601-1732
EXAMINER
TRAN, TONY
ART UNIT PAPER NUMBER
2894
NOTIFICATION DATE DELIVERY MODE
08/16/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE
THE PATENT TRIAL AND APPEAL BOARD
Ex parte ALAN SEABAUGH1
and Susan Fullerton
Appeal 2017-001102
Application 14/212,310
Technology Center 2800
Before MARKNAGUMO, JEFFREY R. ROBERTSON, and
MICHAEL G. McMANUS, Administrative Patent Judges.
NAGUMO, Administrative Patent Judge.
DECISION ON APPEAL
The University of Notre Dame du Lac (“Notre Dame”) timely appeals
under 35 U.S.C. § 134(a) from the Final Rejection2 of all pending claims 1-
20. We have jurisdiction. 35 U.S.C. § 6. We reverse for reasons well-stated
by Notre Dame.
1 The applicant under 37 C.F.R. § 1.46, and hence the appellant under
35 U.S.C. § 134, is the real party in interest, identified as the University of
Notre Dame du Lac (“Notre Dame”). (Appeal Brief, filed 8 March 2016
(“Br.”), 1.)
2 Office Action mailed 15 September 2015 (“Final Rejection”; cited as
“FR”).
Appeal 2017-001102
Application 14/212,310
OPINION
A. Introduction3
The subject matter on appeal relates to nonvolatile memory, i.e.,
memory that “retains stored data even when power is not supplied to the
memory.” (Spec. 1 [0003].) According to the’310 Specification, existing
nonvolatile memories, such as flash drives based on stacked gate structures,
are limited by relatively low write speed and write/erase degradation. {Id.)
Other technologies, such as resistive random access memory (“RRAM”) are
also said to need improvements in writing speed. {Id. at 2-3 [0004].) The
claimed invention, a “random access memory [“RAM”] cell formed by a
transistor incorporating ion storage and a two dimensional crystal”
(Spec. 1 [0002]), is said to provide high density nonvolatile data storage and
high speed reading and writing. The two-dimensional crystal,4 which can be
graphene, forms a conductive channel beneath the top gate of the transistor.
The Specification reveals that high charge carrier densities can be formed in
the two-dimensional crystal by charges proximate to the channel, and thus
the conductivity of the channel can be modulated by varying the distance of
mobile ions to the channel. {Id. at 4 [0012]-5 [0014].) This is done by
adjusting the voltage on the back gate of the transistor. An embodiment of
3 Application 14/212,310, Single transistor random access memory using
ion storage in two-dimensional crystals, filed 14 March 2014, claiming the
benefit of a provisional application filed 15 March 2013. We refer to the
“’310 Specification,” which we cite as “Spec.”
4 The Specification defines two-dimensional crystals as crystals that are
“one monolayer thick so that electron transport in the out-of-plane direction
is obstructed.” {Id. at 7-8 [0018].)
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Application 14/212,310
such a single-transistor RAM cell is illustrated in Specification Figures 1-3,
which are reproduced below.
FIG. 2 FIG. 3
{Fig. 1 shows an equivalent circuit of a single-transistor RAM}
{Fig. 2 shows the transistor in the ON-state (conductive)}
{Fig. 3 shows the transistor in the OFF-state (non-conductive)}
The single transistor RAM cell 1405 6comprises bit line 102, which the
Specification describes as being connected to drain 110 of the transistor [sic:
source 142[6], word line 104 connected to top gate 112, write line 106
connected to back gate 146, and common connection 110 connected to
source 142 [sic: drain 110]. (Spec. 5 [0014].) Source 142 is connected to
drain 110 via 2D crystal channel 108, which may be graphene. {Id. at 7-
5 Throughout this Opinion, for clarity, labels to elements are presented in
bold font, regardless of their presentation in the original document.
6 The circuit diagram 100 in Figure 1 does not label the source or drain of
the transistor, and the description (Spec. 5 [0014]) uses the label 110 for
both the drain and the common connection. It does not appear that these
discrepancies would confuse a person having ordinary skill in the art. For
simplicity, we assume, without deciding, that the circuit diagram 100 in
Figure 1 has the same orientation as Figures 2 and 3. In the words of the
Specification, “[a]s those having ordinary skill in the art will also
understand, some of these statements must be taken in context.” {Id.)
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Application 14/212,310
8 [0018].) Top gate 112 is electrically isolated from channel 108 by
dielectric layer 144. {Id. at 6-7 [0016].) Write line 106 may be used to
change the state of channel 108 by moving ions 148 from one side of
electrically insulating but ion-conducting solid electrolyte 150 to the other
side. {Id. at 10 [0023]—11 [0025].) Ionic conductor 150 is described as a
thin film for small-scale applications. {Id. at 11 [0026].)
When ions 148 (e.g., lithium ions (Li+), and perchlorate (CKAf) drift
through ion conductor 150 to the graphene interface at channel 108, an
electric double layer is formed, which is said to induce sheet carrier densities
in graphene channel 108 as high as about 4 x 1014/cm2 for both electrons and
holes. In the words of the Specification, “[i]n effect, the resistance of the
channel 108 is low when the lithium ions are drifted towards the graphene
channel 108” {Id. at 9 [0021], penultimate sentence), as shown in Figure 2.
This condition is generated when a positive voltage is applied to write
line 106, and thus to back gate 146. {Id. at 10 [0023].) The positive lithium
ions 148 are said to induce electrons from the source associated with bit
line 102 into transistor channel 108 “without exchanging electrons, i.e.,
without oxidizing or reducing, due to the absence of dangling bonds in the
2D conductor.” {Id.) “Moreover, the close proximity of the ions 148 and
induced charge carriers results in a Coulomb force that holds the ions 148 in
place and provides non-volatility.” {Id.) “Conversely,” the Specification
teaches, “the resistance of the channel 108 is high when the lithium ions are
drifted away from the graphene channel 108” {id. at 9 [0021], last sentence),
as shown in Figure 3.
In the words of the Specification, “[depending on the thickness of the
ion conductor and effective velocity of the positive lithium ions 148, the
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Application 14/212,310
speed of the single-transistor RAM cell for reading and writing is in the
nanosecond range.” {Id. at 11 [0025].)
Claim 1 is representative and reads:
A single-transistor random access memory (RAM) cell
comprising:
a conductive path that transmits charge carriers from a
source;
a drain for receiving at least some of the charge carriers;
a channel comprising a two-dimensional (2D) crystal
the channel interposed between the source and the
drain, wherein
the charge carriers flow along the conductive path,
through the channel, to the drain;
a first gate for electrically regulating the flow of the
charge carriers through the channel;
a dielectric isolating the first gate from the channel;
an electrically-insulating ion conductor interposed
between the channel and a back gate,
the conductor comprising a plurality of ions, which are
mobile within the conductor,
the back gate for selectively positioning the plurality of
ions adjacent to the channel by creating an electric field
that directs the plurality of ions,
wherein the plurality of ions, when positioned adjacent to
the channel, induce the charge carriers into the channel,
and
wherein Coulomb forces between the charge carriers in the
channel and the plurality of ions positioned adjacent to the
channel hold the plurality of ions adjacent to the channel.
(Claims App., Br. 14; some indentation, paragraphing, and emphasis added.)
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Application 14/212,310
The Examiner maintains the following grounds of rejection7,8:
A. Claims 1—4, 6-13, 15, 18, and 19 stand rejected under
35 U.S.C. § 102(b) in view of Oezyilmaz.9
Al. Claims 5, 14, 16, 17, and 20 stand rejected under
35 U.S.C. § 103(a) in view of Oezyilmaz.
B. Discussion
The Board’s findings of fact throughout this Opinion are supported by
a preponderance of the evidence of record.
The Examiner finds that Oezyilmaz Figures 1A and 7B10 reproduced
on the following page, teach a single transistor RAM cell 10 meeting all the
limitations of claim 1. (FR 2-3.)
Oezyilmaz describes a memory cell 10 comprising a graphene
layer 16 arranged on a dielectric layer 14 and encapsulated by a thin film
ferroelectric layer 18. (Oezyilmaz 3 [0044].) Graphene layer 16 is
electrically coupled to source region 15 and drain region 17. {Id.) Two
alternative gate regions are formed. One by top electrode 20, which is
coupled to ferroelectric layer 18, and the other by bottom electrode 12,
which is coupled to dielectric layer 14. {Id.)
1 Examiner’s Answer mailed 23 August 2016 (“Ans.”).
8 Because this application claims the benefit of a provisional application
filed before the 16 March 2013, effective date of the America Invents Act,
we refer to the pre-AIA version of the statute.
9 Barbaras Oezyilmaz et al., Graphene memory cell and fabrication
methods thereof U.S. Patent Application Publication 2011/0170330 Al
(2011).
10 The Examiner cites Figure 7A, but reproduces and discusses Figure 7B.
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Application 14/212,310
{Oezyilmaz Figures IB and 7A are shown below}
10
Vw:
-I-
{Figure 1A shows a diagram of a memory cell in cross section}
{Fig. 7A shows a memory cell with charged dielectric layer 14}
Oezyilmaz explains that “[depending on the electric field established
by the gating voltage, charge carriers in graphene can be tuned continuously
from holes to electrons.” {Id. at [0045].) Thus, the charge carrier
concentration as well as the conductivity can be controlled depending on the
bias voltage applied at the gate. {Id.) In order to retain the different
resistance states when the external field is switched off, Oezyilmaz “utilizes
the remnant field of a ferroelectric layer to set a particular resistance state of
the graphene layer.” {Id. at [0046], last sentence.)
The Examiner finds that dielectric layer 14 comprises a plurality of
ions, as shown in Figure 7B, that are interposed between graphene
channel 16 and back gate 12. (FR 3.)
However, as Notre Dame argues (Br. 7), there is no credible evidence
in Oezyilmaz teaching or suggesting that dielectric layer 14 is an ionic
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Application 14/212,310
conductor. Rather, as Notre Dame urges, the weight of the evidence is that
charge migration in dielectric layer 14 arises purely from the motion of
electrons. {Id.) In contrast, the ’310 Specification characterizes the ion
conductor as a solid electrolyte, such as a solid polymer electrolyte (Spec. 6-
7 [0016]; 9 [0021), or a 2D crown ether electrolyte with high ionic
conductivity and low electronic conductivity {id. at 11 [0026]). The
Examiner has not directed our attention to any indication that some broader
meaning is intended that might encompass dielectrics such as the perovskite
oxide disclosed by Oezyilmaz (Oezyilmaz 4 [0051]) or even the electric
dipole flipping that produces asymmetrical remnant polarization in the
ferroelectric layer {id. at [0058], last sentence).
The Examiner makes no findings regarding further limitations recited
in claim 1 or the other claims rejected as anticipated, nor any findings
regarding limitations in other claims rejected as obvious in view of
Oezyilmaz that cure this fundamental defect.
We therefore reverse all rejections of record based on Oezyilmaz.
C. Order
It is ORDERED that the rejection of claims 1-20 is reversed.
REVERSED
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