Ex Parte Schwinn

Board of Patent Appeals and Interferences

Apr 15, 2011

10932730 (B.P.A.I. Apr. 15, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/932,730 09/02/2004 Stephen J. Schwinn ROC920040098US1 2154
7590 04/15/2011
Leslie J. Payne
IBM Corporation, Dept. 917
3605 Highway 52 North
Rochester, MN 55901-7829
EXAMINER
LINDLOF, JOHN M
ART UNIT PAPER NUMBER
2183
MAIL DATE DELIVERY MODE
04/15/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________
Ex parte STEPHEN J. SCHWINN
____________
Appeal 2009-008558
Application 10/932,7301
Technology Center 2100
____________

Before JEAN R. HOMERE, ST. JOHN COURTENAY III, and
CAROLYN D. THOMAS, Administrative Patent Judges.

HOMERE, Administrative Patent Judge.

DECISION ON APPEAL

1 Filed on September 2, 2004. The real party in interest is International
Business Machines Corp. (App. Br. 2.)
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I. STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) (2002) from the
Examiner’s final rejection of claims 1, 3, 5, 6, 8 through 11, 13, 15, 16, and
18 through 24. (App. Br. 4.)2 Claims 2, 4, 7, 12, 14, and 17 have been
cancelled. (Claims App’x.) We have jurisdiction under 35 U.S.C. § 6(b)
(2008).
We affirm-in-part.
Appellant’s Invention
Appellant invented a method and apparatus for pipelined processing
within a processor. (Spec. 1, ll. 4-6.)
Illustrative Claim
Independent claim 1 further illustrates the invention as follows:
1. A method of pipelined processing comprising:

receiving a first instruction in an in-order execution processing
pipeline;

determining first internal operating bits indicative of a
completed state of the first instruction;

starting execution of the first instruction in the in-order
execution processing pipeline;

receiving a second instruction in the in-order execution
processing pipeline before execution of the first instruction completes;

determining second internal operation bits indicative of a
completed state of the second instruction based on the received second
instruction and the first internal operating bits; and

2 All references to the Appeal Brief are to the Appeal Brief filed May 15,
2008.
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starting execution of the second instruction in the in-order
execution processing pipeline before execution of the first instruction
completes using the second internal operation bits.

Prior Art Relied Upon
The Examiner relies on the following prior art as evidence of
unpatentability:
David A. Patterson & John L. Hennessy, Computer Organization &
Design: The Hardware/Software Interface, 2nd ed. (1997), at 118, 368, 496-
97, & 500 (hereinafter “Hennessy”).

Rejections on Appeal
The Examiner rejects the claims on appeal as follows:
Claims 1, 3, 5, 6, 8 through 11, 13, 15, 16, and 18 through 20 stand
rejected under 35 U.S.C. § 112, first paragraph as failing to comply with the
written description requirement.
Claims 1, 3, 5, 6, 8 through 11, 13, 15, 16, and 18 through 20 stand
rejected under 35 U.S.C. § 112, first paragraph as failing to comply with the
enablement requirement.
Claims 1, 3, 5, 6, 8 through 11, 13, 15, 16, and 18 through 24 stand
rejected under 35 U.S.C. § 102(b) as being anticipated by Hennessy.
Appellant’s Contentions
1. Appellant contends that the present Specification provides
adequate support for the claim limitations “operating bits indicating a
completed state,” and “the use of completion indicating bits to determine
second internal operation bits.” (App. Br. 11-14.) Therefore, Appellant
alleges that independent claims 1 and 11 comply with the written description
requirement. (App. Br. 11-14; Reply Br. 3-4.)
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2. Appellant contends that there is more than adequate instruction
in the present Specification to enable an ordinarily skilled artisan to reduce
the claimed invention to practice without resorting undue experimentation.
(App. Br. 17-18.) In particular, Appellant argues that the present
Specification provides adequate instruction to enable an ordinarily skilled
artisan to reduce the following claim features to practice: 1) “operating bits
indicating a completed state;” and 2) “the use of completion indicating bits
to determine second internal operation bits.” (Id. 18-20.) Therefore,
Appellant alleges that independent claims 1 and 11 comply with the
enablement requirement. (App. Br. 17-20; Reply Br. 4.)
3. Appellant disagrees with the Examiner’s position that a PC is a
collection of control bits because the PC controls fetching of instructions.
(Reply Br. 5-6.) Therefore, Appellant argues that Hennessy cannot be
properly relied upon to teach the claimed first and second control bits, let
alone bits based on the first control bits. (App. Br. 20 & 23; Reply Br. 6-7.)
Examiner’s Findings and Conclusions
1. The Examiner finds that Appellant’s Specification discloses
that completion causes the updating of bits, whereas independent claims 1
and 11 recite that the updating of bits indicates completion. (Ans. 19.) That
is, the Examiner finds that Appellant’s Specification does not support
operating bits indicating a completed state because updating bits upon
completion only implies that the bits are updated…not completed. (Id. at
20.) Further, the Examiner finds that the disclosure in Appellant’s
Specification pertaining to how an instruction is to be processed does not
support bits indicating a completed state. (Id.) Additionally, since
inherency cannot be established by mere possibilities, the Examiner finds
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that Appellant cannot rely on inherency to provide support for bits indicating
a completed state. (Id. at 21-22.) Therefore, the Examiner finds that
independent claims 1 and 11 fail to comply with the written description
requirement. (Id. at 19-22.)
2. The Examiner weighs each of the Wands factors individually
and concludes that independent claims 1 and 11 fail to comply with the
enablement requirement. (Id. at 5-7.)
3. The Examiner finds that Hennessy’s disclosure of a PC
amounts to controls bits because the PC controls fetching of instructions.
(Id. at 24-25.) Moreover, the Examiner finds that Hennessy’s disclosure of
utilizing a PC to derive a next PC amounts to utilizing control bits for an
instruction to influence further instructions. (Id.) Therefore, the Examiner
finds that Hennessy’s disclosure teaches the “internal operation bits,” as
recited in independent claims 1, 11, and 24, and the “control bit,” as recited
in independent claim 21. (Id. at 25)

II. ISSUES
1. Has Appellant shown that the Examiner erred in finding that the
claimed invention fails to comply with the written description requirement?
In particular, this issue turns on whether Appellant’s original disclosure
adequately supports the following claim limitations recited in independent
claims 1 and 11:
(a) determining first internal operating bits indicative of a
completed state of the first instruction; and
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(b) determining second internal operation bits indicative of a
completed state of the second instruction based on the received second
instruction and the first internal operating bits.
2. Has Appellant shown that the Examiner in concluding that the
claimed invention fails to comply with the enablement requirement? In
particular, this issue turns on whether Appellant’s original disclosure enables
an ordinarily skilled artisan to reduce to practice without resorting to undue
experimentation the following features recited in independent claims 1 and
11:
1) operating bits indicating a completed state; and
2) the use of completion indicating bits to determine second
internal operation bits.
3. Has Appellant shown that the Examiner erred in finding that
Hennessy anticipates independent claims 1, 11, 21, and 24? In particular,
the issue turns on whether Hennessy describes the following claimed
features:
(a) “internal operation bits,” as recited in independent claims 1, 11,
and 24; and
(b) “control bit,” as recited in independent claim 21.

III. FINDINGS OF FACT
The following Findings of Fact (hereinafter “FF”) are shown by a
preponderance of the evidence.
Appellant’s Specification
FF 1. Appellant’s Specification states that “[u]pon execution
completion of the first instruction, the first instruction may update (e.g.,
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modify or alter) one or more control bits that indicate how an instruction
(e.g., a subsequent instruction) is to be processed.” (Spec. 6, ll. 18-22.)
FF 2. Appellant’s Specification states that “[t]he second set of
internal operation bits is based, in part, on the value of the first set of internal
operation bits.” (Spec. 8, ll. 1-3.) Appellant’s Specification also states that
“[s]imilar to the first instruction execution, upon execution completion, the
second instruction may update (e.g., modify) one or more control bits of that
indicate how instructions (e.g., subsequent instructions) are processed.” (Id.
at ll. 19-23.)
Hennessy
FF 3. Hennessy’s figure 6.52 depicts a PC that points to the memory
location of the next instruction to be fetched from the instruction memory
(44). (500; see also fig. 6.52)

IV. ANALYSIS
35 U.S.C. § 112, First Paragraph—Written Description
Claims 1 and 11
Independent claims 1 and 11 recite, in relevant parts: 1) determining
first internal operating bits indicative of a completed state of the first
instruction; and 2) determining second internal operation bits indicative of a
completed state of the second instruction based on the received second
instruction and the first internal operating bits.
As detailed in the Findings of Fact section above, Appellant’s
Specification discloses updating one or more of the control bits of a first
instruction upon completion of such instruction. (FF 1.) While the
Specification does not explicitly discuss determining first internal operating
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bits that indicate a completed state, we find that an ordinarily skilled artisan3
would have readily ascertained from the cited portion of the original
disclosure that the completion of the first instruction necessarily
encompasses one or more internal operating bites that indicate a completed
state. Thus, we find that Appellant’s original disclosure supports the
limitation of determining first internal operating bits indicative of a
completed state of the first instruction, as recited in independent claims 1
and 11.
Similar to the first instruction, Appellant’s Specification discloses
updating one or more of the control bits of a second instruction upon
completion of such instruction. (FF 2.) While the Specification does not
explicitly discuss determining second internal operating bits that indicate a
completed state, we find that the ordinarily skilled artisan would have
readily ascertained from the cited portion of the original disclosure that the
completion of the second instruction necessarily encompasses one or more

3 “To fulfill the written description requirement [under 35 U.S.C. § 112], the
patent specification must describe an invention in sufficient detail that one
skilled in the art can clearly conclude that the inventor invented what is
claimed.” Kao Corp. v. Unilever U.S., Inc., 441 F.3d 963, 967-968 (Fed.
Cir. 2006) (quoting Cordis Corp. v. Medtronic AVE, Inc., 339 F.3d 1352,
1364 (Fed. Cir. 2003)). Our reviewing court has cautioned, however, that
“[t]he disclosure as originally filed does not … have to provide in haec verba
support for the claimed subject matter at issue.” Cordis Corp., 339 F.3d at
1364 (internal citation omitted). “Although [the applicant] does not have to
describe exactly the subject matter claimed, the description must clearly
allow persons of ordinary skill in the art to recognize that [he or she]
invented what is claimed.” In re Gosteli, 872 F.2d 1008, 1012 (Fed. Cir.
1989) (citations omitted). Put another way, “the applicant must … convey
with reasonable clarity to those skilled in the art that, as of the filing date
sought, he or she was in possession of the invention.” Vas-Cath, Inc. v.
Mahurkar, 935 F.2d 1555, 1563-64 (Fed. Cir. 1991) (emphasis in original).
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internal operating bites that indicate a completed state. Moreover,
Appellant’s Specification discloses that a second set of operation bits is
based, at least in part, on the value of a first set of operation bits. (Id.)
Consequently, we find that the ordinarily skilled artisan would have
understood that the internal operating bits of the second instruction are
based, at least in part, on the internal operating bits of the first instruction.
Thus, we find that Appellant’s original disclosure supports the limitation of
determining second internal operation bits indicative of a completed state of
the second instruction based on the received second instruction and the first
internal operating bits, as recited independent claims 1 and 11. It follows
that Appellant has shown that the Examiner erred in finding that independent
claims 1 and 11 fail to comply with the written description requirement
under 35 U.S.C. § 112, first paragraph.
Claims 3, 5, 6, 8 through 10, 13, 15, 16, and 18 through 20
Since Appellant's original disclosure supports the disputed claim
limitations set forth above, we cannot sustain the Examiner’s rejection of
claims 3, 5, 6, 8 through 10, 13, 15, 16, and 18 through 20 as failing to
comply with the written description requirement under 35 U.S.C. § 112, first
paragraph.
35 U.S.C. § 112, First Paragraph—Enablement
Claims 1, 3, 5, 6, 8 through 11, 13, 15, 16, and 18 through 20
We are not persuaded by Appellant’s argument that the present
Specification provides more than adequate instruction to enable an ordinarily
skilled artisan to reduce the claimed invention to practice without resorting
to undue experimentation. (App. Br. 17-20; Reply Br. 5.) The “enablement
requirement is satisfied when one skilled in the art, after reading the
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specification, could practice the claimed invention without undue
experimentation.” AK Steel Corp. v. Sollac, 344 F.3d 1234, 1244 (Fed. Cir.
2003) (citation omitted). Whether undue experimentation is required is a
conclusion reached by weighing several underlying factual inquiries. In re
Wands, 858 F.2d 731, 736 (Fed. Cir. 1988).
We begin our analysis by noting that the Examiner establishes a prima
facie case that the claimed invention is non-enabling by weighing each of
the Wands factors individually. (Ans. 5-7.) In response, Appellant makes
blanket statements that the claimed invention complies with the enablement
requirement because the present Specification supports both “operating bits
indicating a completed state,” and “the use of completion indicating bits to
determine second internal operation bits.” (App. Br. 18-20; Reply Br. 5.)
Based on the record before us, we find that the weight of the evidence favors
the Examiner’s position since Appellant has not made a bona fide effort to
weigh each Wands factor individually. Therefore, we find that Appellant
has not shown reversible error in the Examiner’s enablement rejection.4
Consequently, we sustain the Examiner’s rejection of claims 1, 3, 5, 6, 8
through 11, 13, 15, 16, and 18 through 20 under 35 U.S.C. § 112, first
paragraph as failing to comply with the enablement requirement.

4 See In re Jung, No. 2010-1019, slip op. at 16 (Fed. Cir. Mar. 28, 2011)
(“Jung argues that the Board gave improper deference to the examiner’s
rejection by requiring Jung to ‘identif[y] a reversible error’ by the examiner,
which improperly shifted the burden of proving patentability onto Jung.
Decision at 11. This is a hollow argument, because, as discussed above, the
examiner established a prima facie case of anticipation and the burden was
properly shifted to Jung to rebut it” . . . “‘reversible error’ means that the
applicant must identify to the Board what the examiner did wrong . . . .”).
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35 U.S.C. § 102(b) Rejection—Hennessy
Claims 1, 11, 21, and 24
Independent claims 1, 11, 21, and 24 recite, in relevant parts, 1)
“internal operation bits;” and 2) “control bit.”
First, we consider the scope and meaning of the claimed terms
“internal operation bits” (claims 1, 11, and 24) and “control bit” (claim 21),
which must be given the broadest reasonable interpretation consistent with
Appellant’s disclosure, as explained in In re Morris, 127 F.3d 1048 (Fed.
Cir. 1997):
[T]he PTO applies to the verbiage of the proposed claims the
broadest reasonable meaning of the words in their ordinary
usage as they would be understood by one of ordinary skill in
the art, taking into account whatever enlightenment by way of
definitions or otherwise that may be afforded by the written
description contained in the applicant's specification.
Id. at 1054. See also Zletz, 893 F.2d 319, 321 (Fed. Cir. 1989) (stating that
“claims must be interpreted as broadly as their terms reasonably allow.”)
Appellant’s Specification states that “[t]he floating point control logic 110
may employ the first set of internal operation bits to execute the first
instruction.” (Spec. 6, ll. 10-12.) Further, Appellant’s Specification states
that “…subsequent instructions may require the modified control bits before
execution of such instructions may start.” (Id. at 7, ll. 5-7.)
Our reviewing court states, “the ‘ordinary meaning’ of a claim term is
its meaning to the ordinary artisan after reading the entire patent.” Phillips
v. AWH Corp., 415 F.3d 1303, 1321 (Fed. Cir. 2005).
Upon review Appellant’s Specification for context, we conclude that
the claimed terms “internal operation bits” (claims 1, 11, and 24) and
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“control bit” (claim 21) are broadly, but reasonably, construed as bits
associated with the execution of an instruction.
The Examiner’s anticipation rejection is premised on the finding that
Hennessey’s disclosure of a PC is a collection of control bits because the PC
controls fetching of instructions. (Ans. 24.) However, we find that the plain
meaning of a PC or program counter is a register that contains the address
(location) of the next instruction to be executed in the program sequence.5
In accordance with this plain meaning, Hennessy discloses a program
counter that points to the memory location of the next instruction to be
fetched from the instruction memory. (FF 3.) Therefore, consistent with our
claim construction above, we find the Examiner’s reading of the claimed
“internal operation bits” (claims 1, 11, and 24) and “control bit” (claim 21)
on Hennessy’s program counter (instruction fetch address) is overly broad
and unreasonable in light of the broadest reasonable interpretation consistent
with Appellant’s Specification. In other words, while Hennessy discloses a
register (PC or program counter) containing the address location of the next
instruction to be executed, such instruction fetch address does not fairly
describe “internal operating bits” (claims 1, 11, and 24) or a “control bit”
(claim 21) indicative of a completed execution state of an instruction. Thus,
we find that the Examiner improperly relied upon Hennessy’s disclosure of a
program counter to describe the claimed “internal operation bits” and
“control bit,” respectively.
Since Appellant has shown at least one error in the rejection of
independent claims 1, 11, 21, and 24, we need not reach the merits of
Appellant’s other arguments. It follows that Appellant has shown that the

5 See Microsoft Press Computer Dictionary, 3rd ed., Microsoft Press, (1997).
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Examiner erred in finding that Hennessy anticipates independent claims 1,
11, 21, and 24.
Claims 3, 5, 6, 8 through 11, 13, 15, 16, 18 through 20, 22, and 23
Since dependent claims 3, 5, 6, 8 through 10, 15, 16, 18 through 20,
22, and 23 also incorporate the claimed features discussed above, we find
that Appellants have also shown error in the Examiner’s rejection of these
claims for the reasons set forth in our discussion of independent claims 1,
11, 21, and 24.

V. CONCLUSIONS OF LAW
1. Appellant has shown that the Examiner erred in finding that
claims 1, 3, 5, 6, 8 through 11, 13, 15, 16, and 18 through 20 fail to comply
with the written description requirement under 35 U.S.C. § 112, first
paragraph.
2. Appellant has not shown that the Examiner erred in concluding
that claims 1, 3, 5, 6, 8 through 11, 13, 15, 16, and 18 through 20 fail to
comply with the enablement requirement under 35 U.S.C. § 112, first
paragraph.
3. Appellant has shown that the Examiner erred in rejecting claims
1, 3, 5, 6, 8 through 11, 13, 15, 16, and 18 through 24 as being anticipated
under 35 U.S.C. § 102(b).
VI. DECISION
1. We reverse the Examiner’s decision to reject claims 1, 3, 5, 6, 8
through 11, 13, 15, 16, and 18 through 20 as failing to comply with the
written description requirement under 35 U.S.C. § 112, first paragraph.
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2. We affirm the Examiner’s decision to reject claims 1, 3, 5, 6, 8
through 11, 13, 15, 16, and 18 through 20 as failing to comply with the
enablement requirement under 35 U.S.C. § 112, first paragraph.
3. We reverse the Examiner’s decision to reject claims 1, 3, 5,
6, 8 through 11, 13, 15, 16, and 18 through 24 as being anticipated under
35 U.S.C. § 102(b).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).

AFFIRMED-IN-PART

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