Ex Parte SCHULTZ

Board of Patent Appeals and Interferences

Apr 12, 2005

09268902 (B.P.A.I. Apr. 12, 2005)

The opinion in support of the decision being entered today
was not written for publication in and
is not binding precedent of the Board.

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
_____________

Ex parte RICHARD SCHULTZ

_____________

Appeal No. 2005-0001
Application No. 09/268,902
______________

ON BRIEF
_______________

Before KRASS, BARRETT and NAPPI, Administrative Patent Judges.

NAPPI, Administrative Patent Judge.

DECISION ON APPEAL

This is a decision on the appeal under 35 U.S.C. § 134 from the

examiner’s rejection of claims 1 through 45. For the reasons stated infra we
affirm-in-part the examiner’s rejection of these claims.

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The Invention
The invention relates to a system for analyzing an electrical characteristic
of wire segments forming a power-bus-grid in an integrated circuit core. The
system performs the steps of mapping the power-bus-grid to the integrated circuit
core, specifying a power zone in the integrated circuit core, calculating an
electrical characteristic of the wire segments relating to the current flowing in the
wire segments and displaying the calculated electrical characteristics. See page
6 of appellant’s specification.
Claim 1 is representative of the invention.
1. A method for analyzing an electrical characteristic of wire
segments forming a power-bus grid in an integrated circuit core, the
method comprising:
mapping the power-bus grid to the integrated circuit core,
wherein said mapping comprises accepting design information of
said integrated circuit core entered in response to a prompt;
accepting information for at least one power zone in the
integrated circuit core;
calculating an electrical characteristic of the wire segments
relating to the current flowing there through; and
displaying the calculated electrical characteristic in the wire
segments.

References

The references relied upon by the examiner are:

Murakata 4,839,821 Jun. 13, 1989

Brasen et al. (Brasen) 5,349,542 Sep. 20, 1994

Mitsuhashi 5,404,310 Apr. 04, 1995

Huddleston et al (Huddleston) 5,498,767 Mar. 12, 1996

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Tuan et al. (Tuan) 5,872,952 Feb. 16, 1999
(filed Apr. 17, 1995)

Cohen et al. (Cohen) 5,914,889 Jun. 22, 1999
(filed Sep. 13, 1996)

Rejections at Issue
Claims 1, 40 and 41 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Mitsuhashi in view of Huddleston.
Claims 2 through 11, 13, 15 through 26, 28, 30 through 38, 42 and 44
stand rejected under 35 U.S.C. § 103 as being unpatentable over Mitsuhashi in
view of Huddleston and Tuan.
Claims 12, 14, 27, 29 and 43 stand rejected under 35 U.S.C. § 103 as
being unpatentable over Mitsuhashi in view of Huddleston, Tuan and Brasen.
Claim 39 stands rejected under 35 U.S.C. § 103 as being unpatentable
over Mitsuhashi in view of Huddleston and Cohen.
Claim 45 stands rejected under 35 U.S.C. § 103 as being unpatentable
over Mitsuhashi in view of Huddleston and Murakata.
Opinion

We have carefully considered the subject matter on appeal, the rejections
advanced by the examiner and the evidence of obviousness relied upon by the
examiner as support for the rejections. We have, likewise, reviewed and taken

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into consideration, in reaching our decision, appellant’s arguments set forth in the
brief1 along with the examiner’s rationale in support of the rejection and
arguments in rebuttal set forth in the examiner’s answer.
With full consideration being given to the subject matter on appeal, the
examiner’s rejections and the arguments of appellant and examiner, for the
reasons stated infra, we sustain the examiner’s rejection of claims 1 through 38
and 40 through 44 under 35 U.S.C. § 103. We reverse the examiner’s rejection
of claims 39 and 45 under 35 U.S.C. § 103.
Grouping of the Claims
At the outset, we note that appellant states, on page 7 of the brief that:
Appellants [sic Appellant] contend[s] that the claims of the
present invention do not stand or fall together. In particular, the
following groups of claims are separately patentable:
Group 1: Claims 1, 40, 41 stand together.
Group 2: Claims 2-5, 42 and 44 stand together.
Group 3: Claims 6-11, 13, 15-26, 28 and 30-35 stand together.
Group 4: Claims 12, 14, 27 and 29 stand together.
Group 5: Claims 36-38 stand together.
Group 6: Claim 39 stands alone.
Group 7: Claim 43 stands alone.
Group 8: Claim 45 stands alone.

37 C.F.R. § 1.192(c) (7) (July 1, 2003) as amended at 62 Fed. Reg. 53196
(October 10, 1997), which was controlling at the time of appellant’s filing of the
brief, states:

1 This decision is based upon the brief submitted November 6, 2003.

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For each ground of rejection which appellant contests and which
applies to a group of two or more claims, the Board shall select a
single claim from the group and shall decide the appeal as to the
ground of rejection on the basis of that claim alone unless a
statement is included that the claims of the group do not stand or
fall together and, in the argument under paragraph (c) (8) of this
section, appellant explains why the claims of the group are believed
to be separately patentable. Merely pointing out differences in what
the claims cover is not an argument as to why the claims are
separately patentable.

Accordingly, we will group the claims as follows:
Group A) claims 1, 40, 41, with claim 1 as representative of that group.
Group B) claims 2-5, 42 and 44, with claim 2 as representative of that
group.
Group C) claims 6-11, 13, 15-26, 28 and 30-35, with claim 6 as
representative of that group.
Group D) claims 12, 14, 27 and 29, with claim 12 as representative of that
group.
Group E) claims 36-38, with claim 36 as representative of that group.
Group F) claim 39.
Group G) claim 43.
Group H) claim 45.
Claim Group A (Claims 1, 40, 41)
Appellant argues, on page 9 of the brief that, “ Mitsuhashi does not teach
or suggest either (i) accepting design information of an integrated circuit core
entered in response to a prompt or (ii) accepting information for at least one

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power zone in the integrated circuit core, as presently claimed.” Further, on page
10 of the brief, appellant argues, “the Examiner admits that Mitsuhashi does not
teach or suggest accepting design information of the integrated circuit core
entered in response to a prompt as presently claimed.”
The examiner states on page 11 of the answer “the invention of
Mitsuhashi is not included to teach accepting design information of an integrated
circuit core entered in response to a prompt as this feature is taught by the
invention of Huddleston.” Further, on pages 12 and 13 of the answer, the
examiner states:
The Examiner maintains that one having ordinary skill in the art would
consider the “sectional regions” of Mitsuhashi to be the “at least one
power zone” since Appellant defines “power zone” as one of “a memory
block, a digital block, a analog block, and a pad cell block” (instant
specification, page 7, lines 10-11) and the “sectional regions” of
Mitsuhashi comprise a plurality of gates and/or transistors making up
analog or digital blocks (Mitsuhashi, column 7, lines 17-27). The Examiner
further asserts that one having ordinary skill in the art would consider
“extracting electrical characteristic parameters, such as the number of
gates, dimensions of transistors, load capacities of the gates, and clock
frequencies related to the gates, [from] each of the sectional regions” (i.e.
power zones) to meet the limitation for accepting information for at least
one power zone.
The Examiner also asserts that the term “accepting” can be broadly
interpreted in accordance with a plurality of definitions, such as “to regard
as true” or “to be able to hold”, and therefore the limitation for “accepting
information for at least one power zone” would also be met by the cited
portions of Mitsuhashi that regard the electric characteristics to be true as
well as hold these characteristics in processing components.

We concur with the examiner’s assessment of the term “accepting” and
the examiner’s finding that Mitsuhashi teaches power zones as claimed, the
issue of accepting design information of an integrated circuit core entered in

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response to a prompt we address infra with respect to Huddleston. We add that
appellant’s specification, on page 14, line 22, equates power zones to areas of
the core, which draw more or less current. We find that Mitsuhashi teaches
setting a theoretical lattice over the circuit and breaks the circuit into sectional
regions (item 11). (See, column 3, lines 35-39 and column 7, lines 58-61). The
amount of current flowing in each of the sectional regions is calculated and the
current in the power-source lines is analyzed. (See column 14, lines 11-21). The
information is used to generate a display of current used in the sectional regions
of the integrated circuit. (See column 10, lines 61-65). Thus, we find that the
sectional regions refer to sections of the integrated circuit that consume power,
which meets the claim limitation of “power zones.”
Appellant further argues, on pages 10 and 11 of the brief that:
[e]ven assuming, arguendo, one skilled in the art would consider the
sectional regions 11 of Mitsuhashi to be similar to the presently claimed at
least one power zone, the Office Action fails to present any objective
evidence or convincing line of reasoning why one of skill in the art would
consider determining the power consumption and a current amount in
each of the sectional regions from the position of each element in a layout
database for the design to be the same as accepting information for at
least one power zone in the integrated circuit core, as presently claimed.
Specifically, determining the power consumption and a current amount in
each of the sectional regions from the position of each element in a layout
database for the design involves post-layout simulation since the layout
database must already exist. However, discovering voltage drop and
electromigration problems after post-layout simulation can add days, if not
weeks, to the design cycle time and can significantly decrease a product’s

competitive advantage. In contrast, accepting design information of an
integrated circuit core entered in response to a prompt and accepting
information for at least one power zone in the integrated circuit core, as
presently claimed, allow a designer to quickly and easily analyze power-

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bus grid designs before a detailed simulation of the IC layout is made
(footnotes omitted).

We are not convinced by appellant’s argument. We find no limitation in
independent claim 1, which differentiates the claimed method from a method that
makes use of a post-layout simulation. Further, we do not find that Mitsuhashi is
limited to a system that uses a post layout simulation. Mitsuhashi teaches, in
column 11, lines 21-27, and 39-44, that the system should be used in conjunction
with the software that generates the floor plan of the circuit. Thus, we find that
Mitsuhashi teaches that the current analysis should be performed concurrent with
the layout of the integrated circuit.
Appellant argues, on page 11 of the brief, “ Huddleston does not cure the
deficiencies of Mitsuhashi. Huddleston is directed to a method for positioning
bond pads in a semiconductor die layout. Huddleston is concerned with the post-
layout period” (footnotes omitted).
As stated supra, we do not find that the method of claim 1 is limited to a
pre-layout period. Thus, we consider it immaterial for the rejection whether
Huddleston is concerned with either a pre or post layout period.
Appellant argues, on page 12 of the brief, that Huddleston is not
analogous prior art and that “Huddleston does not appear to teach or suggest
accepting information for at least one power zone in the integrated circuit core,
as presently claimed.”
In response, the examiner states, on pages 14 and 15, of the answer:

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In this case, the instant invention, Mitsuhashi and Huddleston are all
concerned with improving the designing and laying-out of semiconductor
devices, and are therefore analogous. ….
The Examiner asserts that, as noted above, the invention of
Mitsuhashi does teach accepting information for at least one power zone
of the integrated circuit core. The Examiner further remarks that Appellant
neglects to mention the teachings of Huddleston, specifically prompting
the user to enter values for the length and width of the semiconductor
core/die on which a plurality of cells are to be arranged (i.e. accepting
design information of the integrated circuit core entered in response to a
prompt) (column 4, lines 34-47). Therefore, the combination of Mitsuhashi
and Huddleston teaches all [of] the features of the instant invention as
claimed.

We concur with the examiner’s rationale. We note that claim 1 does not
call for the entry of length and width of the semiconductor in response a prompt,
nonetheless these values are related to the design of the integrated circuit. We
also note that neither the examiner nor the appellant has provided a definition of
what is meant by the claim limitation “in response to a prompt.” One definition
for the term prompt is “to induce an action.”2 The examiner’s statement of the
rejection on page 5 of the answer states, “the program first requires (i.e. prompts)
the user to enter values” thus suggesting that the examiner applied a similar
meaning to the term prompt. Appellant’s specification does not define or

use the term “prompt,” however in numerous instances the appellant’s
specification discusses a user entering design information, see for example page
13, line 24. Thus, we find that the meaning of the claim limitation “in response to
a prompt” means in response to an inducement.

2 Definition from The Random House College Dictionary, Revised Edition 1982.

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While we concur with the examiner, that Huddleston’s input steps teaches
an inducement to input design information, we also find that the inducement to
input design information is implicit in the system of Mitsuhashi. We find that the
system of Mitsuhashi is used in conjunction with a computer aided design (CAD)
program. (See column 5, line 65). Mitsuhashi teaches that the design
information of the core is inputted to the system prior to the current analysis of
the core, i.e. the entry of the design data by a user of the CAD system is a
preliminary step to the current analysis (see column 12, lines 51-55 and column
17 lines 56-57). We find that it is implicit in Mitsuhashi that the input of the
design information for the integrated circuit is in response to an inducement or
prompt. Thus, while we concur with the examiner that Huddleston teaches that
data concerning the design of an integrated circuit core is input in response to a
prompt, we find that this feature of Huddleston is cumulative of Mitsuhashi’s
implicit teaching of inputting design data in response to a prompt.
On page 13 of the brief, appellant argues that the “Office action fails to
provide particular findings as to the reasons a skilled artisan, with no knowledge
of the presently claimed invention, would have selected the cited references for
combination.”
In response, the examiner states, on page 16 of the answer,
[i]n the instant case, the Examiner maintains that based on knowledge
generally available to one having ordinary skill in the art, one would
recognize that since the invention of Mitsuhashi teaches mapping a grid
on a particular surface, it would have been obvious to combine a teaching
of supplying the dimension of that surface because in order to determine

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the dimensions of a grid that is placed on a surface, and insure that the
grid is within the boundaries of the surface, the dimensions of the surface
must be known. The Examiner also maintains that motivation lies in the
Huddleston reference itself because by first requiring that the user input
core/die dimensions on which the mapping is to be constructed, the
combination would have insured correct placement of the components on
the device without allowing an increase in the crucial parameters of the
final core/die size (Huddleston et al., column 1, lines 20-24 and column 1,
line 53 to column 2, line 5).

As stated supra, we find Huddleston’s teaching that data concerning the
design of an integrated circuit core be in response to a prompt to be cumulative
of the teachings of Mitsuhashi and we find that the other limitations of claim 1
which appellant argues differentiate claim 1 from Mitsuhashi, are taught by
Mitsuhashi. Thus, regardless of whether the examiner’s rejection provides
proper motivation to combine Mitsuhashi and Huddleston or not, we will sustain
the examiner’s rejection as appellant’s arguments have not shown a limitation of
representative claim 1 that Mitsuhashi does not teach. In affirming a multiple
reference rejection under 35 U.S.C. § 103, the Board may rely on one reference
alone in an obviousness rationale without designating it as a new ground of

rejection. In re Bush, 296 F.2d 491, 496, 131 USPQ 263, 266-67 (CCPA 1961);
In re Boyer, 363 F.2d 455, 458, n.2, 150 USPQ 441, 444, n.2 (CCPA 1966) .
However, an anticipation rationale may constitute a new ground of rejection. In
re Meyer, 599 F.2d 1026, 1031, 202 USPQ 175, 179 (CCPA 1979); In re Echerd
471 F.2d 632, 635, 176 USPQ 321, 323 (CCPA 1973).
Nonetheless, we find that the examiner, with the motivation provided, has

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established a prima facie case on obviousness. Our reviewing court stated in
Lee, 277 F.3d 1338, 1343, 61 USPQ2d 1430, 1433, that when making an
obviousness rejection based on combination, “there must be some motivation,
suggestion or teaching of the desirability of making the specific combination that
was made by Applicant” (quoting In re Dance, 160 F.3d 1339, 1343, 48 USPQ2d
1635, 1637 (Fed. Cir. 1998)) “The motivation, suggestion or teaching may come
explicitly from statements in the prior art, the knowledge of one of ordinary skill in
the art, or, in some cases the nature of the problem to be solved.” In re Huston
308 F.3d 1267, 1278, 64 USPQ2d 1801, 1810 (Fed. Cir. 2002, citing In re
Kotzab 217 F.3d 1365, 1370, 55 USPQ2d 1313, 1317 (Fed. Cir. 2000). The
examiner has asserted that the motivation to combine stems from the need for a
Mitsuhashi’s system to know the physical dimensions of the integrated circuit.
Further, we find that the nature of the problem to be solved in Mitsuhashi, to
perform a current analysis for the power source wiring, involves analyzing the
flow of current within the wire segments of the integrated circuit. As stated supra
we find that Mitsuhashi teaches that this is performed concurrent with the layout
of the integrated circuit. One of ordinary skill in the art would recognize that the
current enters and exits the chip through bond pads and as such to analyze the
current within the wires extending to the bond pads would also require knowledge
of the location of the bond pads for power and ground. We find that the nature of
the problem to be solved in Huddleston is to find the optimal position of the bond
pads, and that this to be performed in support of the layout of the integrated

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circuit. (See the abstract of Huddleston). Thus, in addition to the reasons
provided by the examiner, we find that the nature of the problem to be solved by
Mitsuhashi and Huddleston provide the motivation to combine the references.
Accordingly, we find that the examiner has made a prima facie case of
obviousness.
Our reviewing court has said, “when the PTO shows sound basis for
believing that the products of the applicant and the prior art are the same, the
applicant has the burden of showing that they are not.” In re Spada, 911 F.2d
705, 708, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990) (citing In re King 801 F2d
1324, 1327, 231 USPQ 136, 138) (Fed Cir. 1986). Appellant’s arguments on
pages 12 and 13, challenging the examiner’s rationale in support of the
motivation to combine the references do not present any facts upon which to
rebut the examiner’s prima facie case of obviousness. Accordingly, we sustain
the examiner’s rejection of the claims in group A, claims 1, 40 and 41.
Claim Group B (Claims 2-5, 42 and 44).
Appellant argues on page 14 of the brief that claims 2-5, 42 and 44
depend upon claim 1, and that Tuan does not “cure the deficiencies of
Mitsuhashi and Huddleston”. Further, on page 15 of the brief, appellant argues;
“the Office Action fails to provide particular findings as to the reasons a skilled
artisan, with no knowledge of the presently claimed invention, would have
selected the cited references for combination.” Specifically, appellant argues, on
pages 15 and 16:

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[t]he conclusory statements that “because the combination would have
provided a process necessary to simulate the constructed trial circuit … in
the process of designing a circuit layout as well as presented a method for
conveniently and quickly analyzing the resulting power bus grid with color
coded sections” and “ the combination would have provided superior
accuracy and more efficient simulation speed” do not adequately address
the issue of motivation to select or combine. (footnotes omitted)

The examiner in response, on page 18 of the answer, asserts that the
appellant has not provided sufficient reasons as to why the motivation provided in
the rejection is improper. Further, the examiner states:
[p]roper motivation exists because the combination of Tuan with the
inventions of Mitsuhashi and Huddleston would have provided a process
necessary to simulate the constructed trial circuit of Mitsuhashi
([Mitsuhashi] column 21, lines 40-45 ) in the process of designing a circuit
layout as well as presented a method for conveniently and quickly
analyzing the resulting power bus grid with color coded sections ([Tuan]
column 12, lines 45-52) while providing superior accuracy and more
efficient simulation speed ([Tuan] column 6, lines 27-29).

We concur with the examiner, as stated supra, with respect to claim 1, we
find that the Mitsuhashi and Huddleston teach the limitations of claim 1. Claim 2
adds the limitation to claim 1 that “the calculated electrical characteristic of the
wire segments is a calculated current density of the wire segments.” We find
that Mitsuhashi teaches, in column 14, lines 6-7, that a trial circuit is converted
from an initial circuit to a model and that analysis portion (item 19) analyses the
electrical characteristics of the initial wiring. The power consumption of each of
the sectional regions is then calculated. (See Mitsuhashi, column 14, lines 21-
22). Mitsuhashi teaches that one of the purposes of this analysis is to evaluate
whether there will be electromigration problems in the wiring (see Mitsuhashi

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column 17, lines 3-11). We find that Mitsuhashi teaches that the current density
of each wire segment is calculated and compared to a maximum current density
as part of an evaluation to determine whether there will be electromigration
problems in the wiring (see Mitsuhashi column 16, lines 9-20). Thus, regardless
of whether the examiner’s rejection provides proper motivation to combine
Mitsuhashi and Huddleston, and Tuan or not , we will sustain the examiner’s
rejection, as appellant’s arguments do not shown a limitation of representative
claim 2 that Mitsuhashi does not teach.
Nonetheless, we find that the examiner’s rejection has provided the
motivation to combine the references. Tuan teaches a system for simulating a
transistor network to calculate current flow (See Tuan, column 2, lines 9-14).
Tuan teaches different methods of calculating current and that the segment
average current method should be used for electromigration analysis as it
provides good accuracy and efficient simulation speed (See Tuan, column 6,
lines 15-32). We find that a skilled artisan would have been motivated to apply
Tuan’s teaching of different methods of simulating current in integrated circuits to
Mitsuhashi’s circuit analysis with the goal of gaining quick and accurate results.
Thus, we find that the examiner has made a prima facie case of obviousness.
Appellant’s arguments on pages 15 and 16 of the brief, challenging the
examiner’s rationale in support of the motivation to combine the references do
not present any facts upon which to rebut the examiner’s prima facie case of

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obviousness. Accordingly, we sustain the examiner’s rejection of the claims in
group B, claims 2-5, 42 and 44.
Group C (Claims 6-11, 13, 15-26, 28 and 30-35)
Appellant states on pages 16 and 17 of the brief that in addition to the
limitations discussed with respect to claim 1, independent claims 6 includes a
limitation of analyzing current density in wire segments for a power bus in an
integrated circuit core, and claim 21 includes the limitation of analyzing the
voltage drop in wire segments for a power bus in an IC. On pages 17 through 21
of the brief, appellant presents the same arguments concerning Mitsuhashi and
the motivation to combine Mitsuhashi and Huddleston discussed supra with
respect to claim 1.
We note, on pages 19 through 21of the brief, appellant only argues the
limitations common to claim 1, and does not argue any of the limitations that
claims 6 and 26 do not share with claim 1. Accordingly, we are not convinced by
appellant’s arguments for the reasons stated supra with respect to claim 1.
On pages 20 and 21 of the brief, appellant presents the same arguments
concerning Tuan and the motivation to combine Tuan discussed supra with
respect to claim 2.
Similarly, we are not convinced by appellant’s arguments for the reasons
stated supra with respect to claim 1. Accordingly, we sustain the examiner’s
rejection of claims in group B, claims 6-11, 13, 15-26, 28 and 30-35.
Group D (claims 12, 14, 27 and 29)

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On page 28 of the brief, appellant argues that the claims in this group
depend either on claim 6 or 21 and that the arguments presented with respect to
claims 6 and 21 also apply. Further, on pages 28 and 29 of the brief, appellant
argues that the office action fails to provide particular findings as to the reasons
to combine.
The examiner rejected the claims in this group under 35 U.S.C. § 103 as
being unpatentable over Mitsuhashi in view of Huddleston, Tuan and Brasen.
(See pages 7 and 8 of the answer). The examiner states on page 8 of the
answer “it would have been obvious … to modify the invention of Mitsuhashi and
Huddleston … because as suggested by Brasen, the combination would have
prevented failure of the circuit by providing a method of insuring that the current
circuit values don’t exceed the electromigration limit (column 5, lines 29-41).”
Claim 12, depends upon claim 6 and adds the limitation “ the operation of
mapping the power-bus grid further includes accepting a length and a width of
the wire segments.” As stated supra, we find that the combination of Mitsuhashi
in view of Huddleston and Tuan teach all of the limitations of claims 6 and 21.
We find that Mitsuhashi teaches, in conjunction with determining the current
density the widths of the power source lines are considered (see column 16, lines
21-22) and in conjunction with the voltage drop analysis the admittance (inverse
of resistance) of the power bus grid is determined (see column 15, lines 10-45).
However, Mitsuhashi does not teach how the admittance (inverse resistance) is
determined. We find that Brasen teaches a system for circuit analysis in the

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power grid of an integrated circuit where the length and width of the power
source grid lines are determined from the layout and used to determine the
current density in, and voltage drop across, the grid lines. (See column 6, lines
6-15 and 26-35). Thus, we find that the skilled artisan would have been
motivated to use Brasen’s system to determine the resistance (admittance) of the
lines in the power source grid, as Mitsuhashi does not disclose a system to
perform the calculations. Accordingly, we sustain the examiner’s rejection of the
claims in group D, claims 12, 14, 27, and 29 .
Group E (Claims 36-38)
On pages 22 though 28 of the brief, appellant presents arguments
directed to the claims in this group. On page 23 of the brief, appellant argues:
Mitsuhashi does not appear to teach or suggest a program storage
medium, readable by a computer, tangibly embodying a program of
instructions executable by the computer for analyzing an electrical
characteristic in wire segments forming a power-bus grid in an
integrated circuit core, where the program comprises instructions
for (i) accepting design information of an integrated circuit core
entered in response to a prompt.

The remainder of appellant’s arguments on pages 23 through 28 of the brief are
the same as presented with respect to claims 1 and 2.
As stated supra, we find that the combination of Mitsuhashi, Huddleston
and Tuan teach the limitations claims 36 and 28 have in common with claims 1
and 2. Regarding the limitation of “ a program storage medium, readable by a
computer, tangibly embodying a program of instructions executable by the
computer,” we find that Mitsuhashi teaches this limitation. As stated supra,

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Mitsuhashi teaches a current analysis system which is performed in conjunction
with a CAD program. As the analysis is performed on the computer we find that
the program to perform the analysis, the computer instructions, are inherently in
a computer readable storage media. Accordingly, we sustain the examiner’s
rejection of claims in group E, claims 36-38.
Group F (claim 39)
Appellant argues on page 31 of the brief that that claim 39 is dependent
upon claim 1 and that the arguments in support of claim 1 also apply. Appellant
also argues that the examiner’s rejection fails to provide a particular finding as to
the reasons that one of ordinary skill in the art would be motivated to combine the
references.
The examiner states on page 9 of the answer:
[t]he invention of Mitsuhashi and Huddleston teaches all [of] the features
of the claimed invention except for including a first mode configured to
select a predetermined set of technology parameters in response to a user
input and a second mode configured to generate custom design
technology parameters in response to user input.
Cohen teaches a method and system for generating a mask layout
of an optical integrated circuit wherein parameters entered by the user to
construct the mask layout, such as device name, core width, and path
lengths (Figures 4A-G), are entered by the user in response to a prompt.
Cohen also teaches that the parameters are shown in a window with
default (i.e. predetermined) values allowing the user to enter custom
parameters or select the predetermined default parameters (column 8,
lines 48-65 and column 15, lines 52-65).
It would have been obvious … to modify the invention of Mitsuhashi
and Huddleston to include a first mode configured to select a
predetermined set of technology parameters in response to a user input
and a second mode configured to generate custom design technology.

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We disagree. Claim 39 includes the limitation “the operation of accepting
design information of said integrated circuit core comprises choosing one of (i) a
first mode… and (ii) a second mode… .” We find that Cohen is concerned with
designing optical integrated circuits. (See title and abstract). Cohen states, “The
design of optical circuits, in contrast to electrical circuits, has considerations
which can not be directly translated from the electrical arts.” (See column 2, lines
60-62). Further, the examiner has not shown why one of ordinary skill would look
to a teaching of how to layout an optical circuit, which does not have a power-
bus-grid, to modify a system for current analysis of the power-bus-grid in an
electronic circuit. Thus, we will not sustain the examiner’s rejection of claim 39.
Group G (claim 43)
Appellant’s arguments directed to the rejection of claim 43, on page 30 of
the brief, are similar to those presented with respect to claims 12, 14, 27 and 29
(Group D).
We are not persuaded by these arguments, and for the reasons stated
supra with respect to claim 12, we sustain the examiner’s rejection of claim 43.
Group H (Claim 45).
Appellant argues on pages 32 and 33 of the brief that claim 45 is
dependent upon claim 1 and that the arguments in support of claim 1 also apply.
Appellant also argues that the examiner’s rejection fails to provide particular
findings as to the reasons that one of ordinary skill in the art would have been
motivated to combine the references.

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On page 10 of the answer, the examiner states:
Murakata teaches an automatic cell-layout arranging method and
apparatus for polycell logic LSI comprising receiving data input including
data representing the types of polycells to be arranged on the chip
substrate, to form a polycell LSI having the function desired by the user,
data specifying the wiring prohibited regions and wiring-permitted regions
of each of the arrays (i.e. power zones), data requesting that the required
specific polycells be connected, and data showing an object function
required (column 4, lines 56-68).
It would have been obvious … to modify… the invention of
Murakata and Huddleston … because Murakata suggests that the
combination would have provided the conventional practice of indicating
wiring prohibited regions for each layer of the wiring lines.
We disagree. Claim 45 includes the limitation “wherein accepting
information for at least one power zone comprises prohibiting wire segments in a
metal layer of at least one of said power zone.” While, we concur that Murakata
teaches a cell layout method where there are wiring prohibit zones. We do not
find that Murakata teaches that the wiring prohibit zones applies to the power-
bus-grid, or that the sectional regions of Mitsuhashi (as discussed supra meet the
claimed power zones) should contain a wiring prohibit zone. Accordingly, we will
not sustain the examiner’s rejection of claim 45.
Conclusion
Only those arguments actually made by appellant have been considered
in this decision. Arguments which appellant could have made but chose not to
make in the brief or by filing a reply brief have not been considered and are
deemed waived by appellant [see 37 CFR § 41.37]. Support for this rule has
been demonstrated by our reviewing court in In re Berger, 279 F.3d 975, 984, 61
USPQ2d 1523, 1528-1529 (Fed. Cir. 2002) wherein the Federal Circuit stated

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that because the appellants did not contest the merits of the rejections in his brief
to the Federal Circuit , the issue is waived. See also In re Watts, 354 F.3d
1362, 1368, 69 USPQ2d 1453, 1458 (Fed. Cir. 2004).

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In view of the forgoing we will sustain the examiner’s rejection of claims 1
through 38 and 40 through 44 under 35 U.S.C. § 103. We reverse the
examiner’s rejection of claims 39 and 45 under 35 U.S.C. § 103.. The decision of
the examiner is affirmed-in-part.
No time period for taking any subsequent action in connection with this

appeal may be extended under 37 CFR § 1.136(a) (1) (iv).

AFFIRMED-IN-PART

ERROL A. KRASS )
Administrative Patent Judge )
)
)
) BOARD OF PATENT
LEE E. BARRETT ) APPEALS AND
Administrative Patent Judge ) INTERFERENCES
)
)
)
ROBERT E. NAPPI )
Administrative Patent Judge )

REN/vsh

Appeal No. 200
Application No.

24
LSI LOGIC CORPORATION
1621 BARBER LANE
MS: D-106
MILPITAS CA 95035