Ex Parte Schilling

Patent Trial and Appeal Board

Jun 17, 2013

11741886 (P.T.A.B. Jun. 17, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte DEAN B. SCHILLING
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Appeal 2011-001875
Application 11/741,886
Technology Center 2100
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Before ELENI MANTIS MERCADER, ERIC B. CHEN, and
MIRIAM L. QUINN, Administrative Patent Judges.

QUINN, Administrative Patent Judge.

DECISION ON APPEAL

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Appellant appeals under 35 U.S.C. § 134(a) (2002) from a final
rejection of claims 1-22, all the claims pending in the application. We have
jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

STATEMENT OF THE CASE
The invention relates to a system and method for timing
improvements by dual output synchronizing a buffer. Spec., Abstract.
Details of the appealed subject matter, with disputed claim language
emphasized, are recited in representative independent claim 1, reproduced
below from the Claims Appendix of the Appeal Brief:
1. A system, comprising:
a plurality of multi-bit busses;
a synchronizing FIFO buffer, the FIFO buffer comprising:
an input port that receives input data;
a plurality of registers into which the input data is
latched;
at least two output ports, driven by a select signal, out
of which the input data is latched;
wherein the data is latched out of the two output ports
alternatingly based on an even/odd control signal, thereby
extending a timing budget for synchronizing the plurality of
multi-bit busses;
a logic gate branch coupled to each of the output ports; and
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a mux that receives each logic gate branch output and forwards
one of said logic gate branch outputs based on the even/odd read
control signal.

As evidence of unpatentability of the claimed subject matter, the
Examiner relies on the following references at pages 3 to 13 of the Answer:
Tang US 2003/0164836 A1 Sept. 4, 2003
Chakravarthy US 2004/0160845 A1 Aug. 19, 2004
Branch Definition, DICTIONARY OF COMPUTING, http://www.credore-
ference.com/entry/acbcomp/branch (last visited Jun. 18, 2010).
The Examiner provides the following grounds of rejection, of which
Appellant seeks review:
(1) Claims 1-20 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Chakravarthy (Ans. 3-10); and
(2) Claims 21 and 22 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Chakravarthy and Tang (Ans. 11-13).
ISSUES
Based on Appellant’s arguments, the dispositive issues on appeal are:
(a) Whether the Examiner erred in rejecting independent claims 1, 7, and
13 because Chakravarthy does not disclose “a logic gate branch,” as
recited in claim 1, and “logic branch[es],” as recited in claims 7 and
13 (App. Br. 11-12);
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(b) Whether the Examiner erred in rejecting independent claims 1, 7, and
13 because Chakravarthy does not disclose the “even/odd [read]
control signal,” as recited in those claims (App. Br. 12); and
(c) Whether the Examiner erred in rejecting dependent claims 21 and 22
because the combination of Chakravarthy and Tang is improper (App.
Br. 13).
ANALYSIS
We have reviewed the Examiner’s rejection in light of Appellant’s
contentions. Further, we have reviewed the Examiner’s response to
Appellant’s arguments. Appellant did not argue separate patentability of the
dependent claims 2-6, 8-12, and 14-20. Therefore, except for our ultimate
decision, these claims are not discussed further herein.
LOGIC BRANCH ISSUE
Appellant contends that “Chakravarthy does not teach the claimed
logic branches and a mux that receives each logic branch output as in
claim 1.” App. Br. 11. More particularly, Appellant argues that the output
“wires” of the Data Select (i.e., item 303 in Fig. 3 of Chakravarthy) is not
the same as the claimed “logic gate branch” and “parallel logic branches,”
because these are “more than mere lines/wires.” Reply 3. Appellant states
that “logic gates” or “logic” is a term of art that “refers to various hardware
components that operate on received inputs in various ways (AND/OR/NOT
gates) and with various delays.” Reply 3. We do not agree with Appellant’s
conclusions that the Examiner erred.
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First, since the dispute centers on the scope of claim terms, we now
construe the disputed claim language. Claim 1 recites “a logic gate branch
coupled to each of the output ports.” Similarly, claim 7 recites that “data is
latched out of the two output ports alternatingly to external parallel logic
branches,” and claim 13 recites “providing a parallel logic branch from each
latched FIFO output.” The noun of the term is the “branch,” which is
modified by the phrases “logic gate” (in claim 1) and “logic” (in claims 7
and 13). The “branches” are mentioned in paragraph 16 of the Specification
by stating that “time savings are the result of having two parallel branches of
logic off of each of the out_data ports 120, 122,” and that the branches “may
then be combined in a mux . . . .” Spec. ¶ [0016]. Appellant admits that
these “branches” are not depicted in any of the Specification’s drawings.
Reply 2. We find that Appellant has not defined the “branch” terms as
having specialized meaning. Therefore, we give the terms the broadest
reasonable interpretation in light of the Specification, guided by the ordinary
meaning.
The ordinary meaning of “branch” is “a line linking one or more
devices to the main network.” See Ans. 14 (relying on a definition of
“branch” from the Dictionary of Computing). The addition of the modifiers
“logic gate” and “logic” refine the meaning of “branch” by associating the
“line linking one or more devices” to logic gates and logic. Therefore, we
construe the “logic gate branch” and “logic branch” terms to mean: a line
linking one or more devices to a logic gate or logic. This definition is
consistent with the Specification, which describes the “branches” as being
“combined in a mux” and “fed to a latch.” Spec. ¶ [0016]. That is, the lines
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(branches) converge at the multiplexer (mux), which feeds the data carried
by those lines to the latch.
Guided by our construction of the “branch” terms, we do not find
error in the Examiner’s finding that Chakravarthy meets those limitations.
The Examiner finds, and we agree, that the parallel lines Even Data out and
Odd Data out are lines linking the output ports of the Data Select 303 device
in Chakravarthy to the MUX 306. Ans. 14 (pointing to Chakravarthy, fig.3).
The Chakravarthy multiplexer or MUX receives, at the end of the line, the
data carried by those lines, meeting thus the limitation of the mux
“receiv[ing] each logic gate branch output,” as recited in claim 1, and
similarly recited in claims 7 and 13.
Therefore, we are not persuaded by Appellant’s arguments that the
Examiner erred in finding that Chakravarthy meets the “branch” limitations,
as recited in independent claims 1, 7, and 13.
CONTROL SIGNAL ISSUE
Appellant next contends that Chakravarthy’s MUX 306 “is not
controlled by the same even/odd read control signal as the data select circuit
303,” in contravention with the language of the independent claims. App.
Br. 12. In Appellant’s view, the different control signals in Chakravarthy do
not teach the recited “even/odd control signal.” We are not persuaded by
Appellant’s arguments.
Claim 1 recites that the “data is latched out of the two output ports
alternatingly based on an even/odd control signal” and that the mux
“forwards one of said logic branch outputs based on the even/odd read
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control signal.” Claim 13 recites similar limitations, and claim 7 differs
only in that it recites that the “even/odd control signal . . . controls” the
mux. The Examiner finds that the Data Out Control signal shown in Figure
3 of Chakravarthy is the claimed even/odd control signal. Ans. 4, 7 and 8.
Figure 3 clearly shows the Data Out Control signal acting on the MUX 306.
Chakravarthy, fig.3. Further, to describe how the Data Out Control signal is
related to the Even Data out and Odd Data out (output ports), Chakravarthy
states: “The contents of ‘Even Data out’ are assigned to ‘Data out’ when the
Data out control [signal]’ is at logic ‘0’, while contents of the ‘Odd Data out’
are assigned to ‘Data out’ when the ‘Data out control [signal]’ is at logic
‘1’.” Chakravarthy ¶ [0025] (cited by Examiner Ans. 4, 6, and 8).
We find that Figure 3 and the passage cited by the Examiner (Ans. 4)
disclose the Data Out Control signal controlling the output of the multiplexer
in Chakravarthy and that the latching of data of the output ports of the Data
Select device, item 303, is based on the Data Out Control signal.
Appellant’s argument that the Examiner finds the limitation of the even/odd
control signal is met by a signal other than the Data Out Control Signal is
unpersuasive as it does not address the grounds of the rejection.
Consequently, we find no error in the Examiner’s findings and
conclusions that Chakravarthy discloses the disputed limitations.
REJECTION OF CLAIMS 21 AND 22 OVER CHAKRAVARTHY AND TANG
Appellant contends the combination of Chakravarthy and Tang, in the
rejection of claims 21 and 22, is in error because the teachings are
incompatible and the combination improperly changes the principle of
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Chakravarthy’s operation. App. Br. 13. Appellant argues that using gray
code counters, as taught in Tang, would change Chakravarthy’s purpose of
reducing FIFO latency. App. Br. 13.
We do not agree with Appellant’s contention. First, we are not
persuaded that the combination of Chakravarthy and Tang is incompatible
because the Examiner finds that Chakravarthy would benefit from Tang’s
gray code counters to reduce noise in Chakravarthy’s state machine.
Ans. 17 (relying on Tang, ¶ [0006]). Furthermore, we are not persuaded that
Chakravarthy’s principle of operation would improperly change by the
implementation of gray code counters. Specifically, Appellant misstates the
purpose of Chakravarthy, which describes providing “a method and
apparatus for reducing access time in FIFOs without introducing any latency
overhead.” Chakravarthy, ¶ [0007] (emphasis added). The purpose is not to
reduce latency, is to reduce access time. And it achieves this by “look ahead
reading” or fetching the next word from the FIFO and assigning it to one of
the data out buses (Even data out or Odd data out). Chakravarthy, ¶ [0055].
Accordingly, Appellant has not provided sufficient evidence to persuade us
that Chakravarthy’s “look ahead reading” would be improperly changed by
the addition of gray code counters.
Therefore, we do not find error in the Examiner’s combination of
Chakravarthy and Tang.
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CONCLUSION
We conclude that Appellant has not shown error in the Examiner’s
findings and conclusions concerning the anticipation of independent claims
1, 7, and 13 by Chakravarthy and the obviousness of dependent claims 21
and 22 over the combination of Chakravarthy and Tang. Therefore, we
sustain the rejection of independent claims 1, 7, and 13 under 35 U.S.C.
§ 102(b) as anticipated by Chakravarthy, and we group dependent claims 2-
6, 8-12, and 14-20 with claims 1, 7, and 13. See 37 C.F.R.
§ 41.37(c)(1)(vii). Furthermore, we sustain the rejection of dependent
claims 21 and 22 under 35 U.S.C. § 103(a) over Chakravarthy and Tang.
DECISION
We affirm the Examiner’s decision to reject claims 1-22.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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