Ex Parte Sartore

Patent Trial and Appeal Board

Jul 27, 2016

12566086 (P.T.A.B. Jul. 27, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/566,086 0912412009 Ronald H. Sartore
29586 7590 07/29/2016
FSPLLC
431 H Street
Crescent City, CA 95531
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
FSP0558 1733
EXAMINER
TALUKDAR, ARVIND
ART UNIT PAPER NUMBER
2132
NOTIFICATION DATE DELIVERY MODE
07/29/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
charles.a.mirho@fspllc.com
PA TENTS@FSPLLC.COM
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte RONALD H. SARTORE
Appeal 2015-001283
Application 12/566,086
Technology Center 2100
Before JOHN A. JEFFERY, BRADLEY W. BAUMEISTER, and
DENISE M. POTHIER, Administrative Patent Judges.
JEFFERY, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner's
decision to reject claims 1-25. We have jurisdiction under 35 U.S.C. § 6(b ).
We affirm.
Appeal 2015-001283
Application 12/566,086
STATEMENT OF THE CASE
Appellant's invention concentrates wear to cause a portion of non-
volatile memory to wear out sooner. Spec. i-f 18. Repeated erasure and
writing of certain nonvolatile-memory locations---e.g., a flash-device
block-will eventually render those locations unusable. Id. i-f 2.
Known wear-leveling approaches evenly distribute the physical location of
writes to extend a memory device's life. Id. i-f 3. In contrast, wear-
concentration logic targets certain memory devices for accelerated wear.
Id. i-f 22. When a memory device is nearing or at the end of its useful life,
some embodiments isolate the device from system power or signal the
operator to replace the device. Id. Claim 1 is illustrative:
1. A memory system comprising:
a volatile memory;
a non-volatile memory;
the volatile memory configured as a buffer memory for
the nonvolatile memory; and
wear concentration logic to target one or more selected
devices of the nonvolatile memory for accelerated wear, the
wear concentration logic comprising memory direction logic to
concentrate memory write-backs from the volatile memory to
the non-volatile memory within the targeted devices
preferentially over the other areas or [sic] the non-volatile
memory, 1 thus causing the non-volatile memory to wear out
1 Because independent claims 1, 15, and 21 recite "other areas or the non-
volatile memory" (emphasis added), these claims confusingly require
writing back to non-volatile memory "preferentially over" the same non-
volatile memory. We, therefore, read the phrase "the other areas or the non-
volatile memory" (emphasis added) as "the other areas of the non-volatile
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Application 12/566,086
over time in a uneven manner, wherein the memory direction
logic is replacement logic for data stored in the volatile
memory.
THE REJECTIONS
The Examiner rejected claims 1-5, 7-11, 13-19, 21-23, and 25 under
35 U.S.C. § 103(a) as unpatentable over Chilton (US 7,865,761 Bl; patented
Jan. 4, 2011) and Chen (US 2010/0306448 Al; published Dec. 2, 2010).
Final Act. 3-7. 2
The Examiner rejected claims 6, 12, 20, and 24 under 35 U.S.C.
§ 103(a) as unpatentable over Chilton, Chen, and Biswas
(US 2008/0282023 Al; published Nov. 13, 2008). Final Act. 7-8.
THE OBVIOUSNESS REJECTION OVER CHILTON AND CHEN
Contentions
The Examiner finds that Chilton discloses every recited element of
claim 1 except for wear-concentration logic comprising memory-direction
logic to concentrate memory write-backs, but relies on Chen as teaching this
feature in concluding that the claim would have been obvious. Final Act.
3-5. In particular, the Examiner finds that Chilton's DRAM3 corresponds to
the recited volatile memory. Id. at 4 (citing Chilton, col. 11, 11. 3-5). The
memory." We leave to the Examiner to determine whether "the other areas"
expressed as an alternative to "the non-volatile memory" is indefinite.
2 Throughout this opinion, we refer to (1) the Final Rejection mailed
December 19, 2013 ("Final Act."); (2) the Appeal Brief filed July 21, 2014
("App. Br."); (3) the Examiner's Answer mailed August 28, 2014 ("Ans.");
and (4) the Reply Brief filed October 28, 2014 ("Reply Br.").
3 DRAM stands for dynamic random access memory. See Spec. i-fi-f 18, 22.
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Examiner further finds that Chilton's flash memory corresponds to the
recited non-volatile memory. See Final Act. 4 (finding that Chilton's
DRAM is a cache for flash memory); see also Ans. 3 (discussing DRAM as
a buffer for flash memory). According to the Examiner, Chilton uses
wear-concentration logic to target this non-volatile memory for uneven
wear. Final Act. 4 (citing Chilton, col. 2, 11. 38--45). The Examiner
concludes that it would have been obvious to concentrate Chen's
write-backs to a particular area for uneven wear. Final Act. 4--5; see also
Ans. 4 (discussing concentrating write-backs to a particular area).
Appellant argues that Chilton cannot be modified with Chen to use
write-backs from Chilton's volatile memory 46 to the flash modules 48 for
wear concentration. App. Br. 9--12. 4 According to Appellant, Chilton lacks
a write-back mechanism between volatile memory 46 and the flash modules
58. Id. at 10-11. In Appellant's view, Chilton does not teach that
write-backs from memory 46 could be used for wear concentration because
Chilton's controller 56 concentrates writes from devices 44 to and from flash
58. Id. Accordingly, Appellant concludes that Chilton teaches away from
the claimed system (id. at 10), and Examiner's rejection is based on
impermissible hindsight (id. at 11 ).
In responding to the Examiner's citation to Chilton's column 11,
Appellant argues that Chilton uses DRAM as a write cache, not for wear
concentration. Reply Br. 2. According to Appellant, Chilton's main
controller 52-not flash memory controller 56---performs wear
4 Although the Appeal Brief is not paginated (unlike the Reply Brief), we
nonetheless refer to the Appeal Briefs pages in the order that they appear in
the record.
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Application 12/566,086
concentration. Id. at 2-3 (citing Chilton col. 5, 11. 15-33). Appellant argues
that Chilton's wear concentration is not implemented as memory controller
56's RAM-cache-replacement policy. Reply Br. 3.
In Appellant's view, Chilton uses a cache for wear mitigation. Id.
Appellant argues that Chilton's wear concentration has already been effected
by the time the writes reach the cache. Id.
Appellant further contends that Chen only writes-back after a certain
time expires, and describes the opposite of wear concentration: wear
leveling. App. Br. 10 (citing Chen i-fi-130, 42); see also Reply Br. 4.
Appellant also argues that Chen's memory flush is not a directed
replacement, and this flush does not distribute the write-backs. Reply Br. 4.
Issue
Under§ 103, has the Examiner erred in rejecting claim 1 by finding
that Chilton and Chen collectively would have taught or suggested the
recited wear-concentration logic?
Analysis
On this record, we find no error in the Examiner's obviousness
rejection of representative claim 1.
In the principal Brief, Appellant's arguments are based on an
assumption that, in the rejection, Chilton's memory 46 corresponds to the
recited volatile memory. App. Br. 9-12. But the Examiner finds that
Chilton's DRAM cache corresponds to the recited volatile memory.
Final Act. 4 (citing Chilton, col. 11, 11. 3-5). Chilton's memory modules 24
includes a DRAM cache. Chilton, col. 11, 11. 3-5. By contrast, Chilton's
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Application 12/566,086
memory 46 is in a different module---control module 26. See, e.g., id.
Fig. 2. So Appellant's discussion of volatile memory 46 (App. Br. 9-12) is
not germane to the Examiner's rejection, which is based on a different
rationale.
Likewise, Appellant's diagram omits Chilton's DRAM cache,
depicting a disk instead. See id. at 9; Reply Br. 2. But the Examiner's
rejection does not discuss Chilton's flash-disk arrangement as being
germane to the wear concentration at issue. See Final Act. 4. Because
Appellant's arguments do not squarely address the Examiner's basis for
rejecting the claim, Appellant's arguments contained in the principal Brief
(see App. Br. 9-12) are unpersuasive.
In the principal Brief, Appellant also argues that Chilton's
wear-concentration logic is in the local flash controllers 56. Id. at 11. Yet,
Appellant contradicts this argument in the Reply Brief by contending that
the main controller 52 of the control module 26---not memory controller
56---performs wear concentration. Reply Br. 3 (citing Chilton, col. 5, 11. 15-
33).
Even this later argument (Reply Br. 2-3) is unpersuasive because it is
not commensurate with the scope of the claim. Claim 1 requires that the
wear-concentration logic concentrates memory write-backs, as recited.
Claim 1, however, does not recite where the wear-concentration logic is
stored or executed. Accordingly, we see nothing in claim 1 that precludes
the wear-concentration logic from being carried out by, among other things,
Chilton's main controller 52.
Like the recited wear-concentration logic, Chilton's main controller
52 biases memory operations to wear out non-volatile semiconductor
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memory---e.g., flash memory-unevenly. Chilton col. 5, 11. 15-33, cited in
Reply Br. 3; see also Chilton, col. 2, col. 38--45, cited in Final Act. 4. In one
embodiment, memory module 24 uses volatile memory (e.g., DRAM)
intermixed with non-volatile flash memory. Chilton, col. 10, 1. 66 - col. 11,
1. 3. In particular, control module 26 in memory module 24 uses the DRAM
as a cache for write data, reducing the number of writes to non-volatile flash
components. Id. col. 11, 11. 4---6, cited in Final Act. 4.
Regardless of the wear-concentration's origin, Chilton's non-volatile
flash components are nonetheless targeted for uneven wear, as recited in
claim 1. Chilton, col. 2, col. 38--45. That is, Chilton's main controller 52
need not act as a RAM cache, itself, as argued. See Reply Br. 3. Claim 1
only requires that main controller 52, in executing the wear-concentration
logic, causes memory write-backs to be concentrated, as recited---even if the
memory is indirectly targeted through an intervening cache component.
By using DRAM as a cache for writes to the flash components,
Chilton uses the DRAM-i.e., volatile memory-as a cache between the
flash and main controller 52. See Chilton, col. 11, 11. 4---6. Accordingly,
writes to DRAM must cause some data to be written later to Chilton's flash
components. See id. In other words, the DRAM does not prevent data
writes to Chilton's flash components. See id. Rather, the DRAM mitigates
wear to the flash, as acknowledged by Appellant (Reply Br. 3). Although
the writes go through a DRAM cache, Chilton's flash components are
nonetheless the ultimate destination for the data, and thus, the
wear-concentration target. See Chilton col. 11, 11. 4---6.
As for how Chilton's data gets to the flash components from the
DRAM cache, the Examiner finds that Chilton does not disclose
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write-backs. See Final Act. 4. But we see no error in the Examiner's
citation to Chen for this feature. See id. Here, the Examiner does not
propose using Chen's wear leveling (see id.), as discussed by Appellant.
App. Br. 10 (citing Chen i-f 42). Rather, the Examiner cites Chen for the
limited purpose of showing memory write-backs between volatile and
non-volatile memory, and that those write-backs cause wear. Final Act. 4--5.
Specifically, Chen first writes incoming data to write cache 102.
Chen i-f 24. Write cache 102 is volatile memory. Id. i-f 27. Later, auto-flush
engine 212 writes data back to non-volatile memory. Id. i-fi-124, 30. So, if
writes cause volatile-to-non-volatile-memory write-backs, the Examiner's
reasoning that concentrated writes will cause concentrated write-backs is
plausible. See Ans. 4 (discussing adapting auto-flush for concentrated write-
backs ). That is, by the Examiner's reasoning (id.), Chilton's main controller
52's concentrated writes (Chilton col. 2, 11. 38--45) would also cause
auto-flush engine 212 (Chen i-f 30) to concentrate memory write-backs to the
targeted device.
We see nothing on this record to suggest that this modification would
require substantial or non-obvious re-engineering, as argued. Reply Br. 3.
Appellant has not shown, for example, that incorporating Chen's auto-flush
engine 212 would have been uniquely challenging or otherwise beyond the
level of ordinarily skilled artisans. See Leapfrog Enters., Inc. v. Fisher-
Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007). Nor has Appellant shown
that the Examiner's proposed combination would render the prior art
unsuitable for its intended purpose to teach away from such an approach.
See In re Gordon, 733 F.2d 900, 902 (Fed. Cir. 1984).
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Rather, the Examiner's combination uses Chen to perform the same
function in the combination as it does separately-writing back data from
volatile to non-volatile memory (Chen i-f 30}-with no change in operation.
In this way, the Examiner combines prior art elements according to known
methods to yield predictable results-an obvious combination. See KSR
Int'! Co. v. Teleflex, Inc., 550 U.S. 398, 416 (2007). Accordingly, we are
unpersuaded by Appellant's arguments about the combinability of the
references or Appellant's contentions that the Examiner engaged in
impermissible hindsight. See App. Br. 9-12; Reply Br. 3--4.
Furthermore, we are unpersuaded by Appellant's arguments against
Chen individually. See App. Br. 1 O; Reply Br. 3--4. In particular, the
Examiner does not rely solely on Chen's memory flush as a replacement
policy, as Appellant argues (Reply Br. 4). Nor does the Examiner find that
performing a memory flush implies or inherently requires concentrated
write-backs, as Appellant argues (id.). Such individual attacks do not show
non-obviousness where, as here, the Examiner's rejection is based on the
Chilton-Chen combination collectively teaching the recited concentrating
memory write-backs and replacement policy. See Final Act. 4--5.
Accordingly, we sustain the Examiner's rejection of claim 1, and
claims 2-5, 7-11, 13-19, 21-23, and 25, not argued separately with
particularity. See App. Br. 9-12; Reply Br. 2--4.
THE OBVIOUSNESS REJECTION OVER CHILTON, CHEN, AND
BISWAS
In arguing that Chilton does not move data out of target devices and
erase those devices when full, Appellant did not identify a particular claim
apart from summarily asserting that this argument applies to "some of the
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dependent claims." App. Br. 10. But an Appeal Brief filed by a registered
practitioner, as is the case here, requires a separate subheading that identifies
the claims by number for any claims argued separately or as a subgroup.
37 C.F.R. § 41.37(c)(l)(iv).
Nevertheless, we address this argument. Claims 6, 12, 20, and 24
recite, in part, logic to copy data from a device and erase the device after
copying. So to the extent that the argument applies to claims 6, 12, 20, and
24 (see App. Br. 10), the argument does not persuasively rebut the
Examiner's rejection.
In particular, Appellant argues that Chilton does not move data out of
target devices and erase those devices when full. Id. Appellant further
argues that doing so would not make sense for Chilton, which drives the
contents of the flash from a disk. Id.
But here, the Examiner did not rely on Chilton for this purpose.
Final Act. 7. Rather, the Examiner cites a third reference-Biswas-in
concluding that this feature would have been obvious. Id. (citing Biswas
i-fi-16, 52). Therefore, Appellant's argument (App. Br. 10) is unpersuasive
because it amounts to an individual attack against Chilton, and does not
address the Examiner's reliance on Biswas in connection with the limitation
at issue.
Moreover, like the above-discussed arguments, Appellant's argument
focuses on the flash-to-disk operation (see id.) without discussing the
Examiner's reliance on Chilton's DRAM cache embodiment (see
Final Act. 4). Accordingly, this argument (App. Br. 10) is unpersuasive for
the additional reason that it does not squarely address the Examiner's
rationale.
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Accordingly, we sustain the Examiner's rejection of claims 6, 12, 20,
and 24.
DECISION
The Examiner's decision rejecting claims 1-25 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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