Ex Parte Saremi

Patent Trial and Appeal Board

Sep 16, 2016

13732527 (P.T.A.B. Sep. 16, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
131732,527 01102/2013
105219 7590 09/20/2016
GARLICK & MARKISON (SW)
ATTN: MELANIE MURDOCK
P.O.Box 160727
Austin, TX 78716
FIRST NAMED INVENTOR
Thomas Jefferson Saremi
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
MOR016US 8618
EXAMINER
CHEN,CAIY
ART UNIT PAPER NUMBER
2425
NOTIFICATION DATE DELIVERY MODE
09/20/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
MMURDOCK@texaspatents.com
ghmptocor@texaspatents.com
bpierotti@texaspatents.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte THOMAS JEFFERSON SAREMI
Appeal2015-005821
Application 13/732,527
Technology Center 2400
Before JOHN A. EVANS, CATHERINE SHIANG, and
JAMES W. DEJMEK, Administrative Patent Judges.
EV ANS, Administrative Patent Judge.
DECISION ON APPEAL
Appellant1 seeks our review under 35 U.S.C. § 134(a) from the
Examiner's final rejection of Claims 1-15. App. Br. 2. We have
jurisdiction under 35 U.S.C. § 6(b ).
We REVERSE.2
1 The Appeal Brief identifies Morega Systems, Inc., as the real party in
interest. App. Br. 2.
2 Rather than reiterate the arguments of Appellant and the Examiner, we
refer to the Specification (filed Jan. 2, 2013, "Spec."), the Final Action
Appeal2015-005821
Application 13/732,527
STATEMENT OF THE CASE
The claims relate to an audio file interface. See Abstract.
Claims 1 and 9 are independent. An understanding of the invention
can be derived from a reading of exemplary Claim 1, which is reproduced
below with some formatting added:
1. A client device comprising:
a network interface, coupled to receive media content and
server time data via a network, the media content protected by
digital rights management data;
a processing device, coupled to the network interface, for
executing a digital rights management application for validating
playback of media content based on the digital rights
management data and further based on secure clock data,
wherein the processing device includes a processor clock that
generates processor clock data;
a memory, coupled to the processing device, for storing
the secure clock data, the digital rights management application
and the digital rights management data; and
a system clock, coupled to the processing module, for
generating system clock data;
wherein the digital rights management application
generates the secure clock data based on the server time data,
the system clock data and the processor clock data.
(mailed Aug. 19, 2014, "Final Act."), the Appeal Brief (filed Dec. 19, 2014
"App. Br."), the Examiner's Answer (mailed Mar. 27, 2015, "Ans."), and the
Reply Brief (filed May 13, 2015, "Reply Br.") for their respective details.
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Appeal2015-005821
Application 13/732,527
References and Rejections
Claims 1-15 stand rejected under 35 U.S.C. § 102 (b) as anticipated
by Parks et al. (US 2003/0233553 Al, Dec. 18, 2003) (hereinafter "Parks"). 3
Final Act. 3-5.
ANALYSIS
We have reviewed the rejections of Claims 1-15 in light of
Appellant's arguments that the Examiner erred. We are persuaded that
Appellant identifies reversible error as detailed below. We provide the
following explanation to highlight and address specific arguments and
findings primarily for emphasis. We consider Appellant's argument as
presented in the Appeal Brief, pages 3-7.
CLAIMS 1-15
Appellant argues Claims 1-15 as a group and specifically argue
independent Claim 1. App. Br. 7. We, therefore, limit our discussion to the
common elements of the claims. See 37 C.F.R. § 41.37(c)(l)(vii) (2007).
Processor clock data generated by a processor clock.
In view of Appellant's arguments, we find the dispositive issue is
whether Parks discloses "a processor clock that generates processor clock
3 The Examiner refers to the reference as "Park." See Final Act. 3.
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Appeal2015-005821
Application 13/732,527
data," as recited in independent Claim 1 (and as commensurately recited in
independent Claim 9).
The Examiner finds Parks discloses a processing device including a
"processor clock that generates processor clock data." Final Act. 3 (citing
Parks, Fig. 4, i-fi-1 42--49).
Appellant contends Parks discloses a "secured clock 22" and that the
display time is generated from the secured clock and "a time offset 64."
App. Br. 5---6 (citing Parks i-fi-137, 38). According to Appellant, the time
offset is variously described as a time value that is adjustable by the user, or
a predetermined value(s) that may correspond to a time difference that may
arise from time zones. Id. at 6. Appellant argues the Specification discloses
the claimed processor clock data:
As time elapses, the accuracy of the server's last saved time
diminishes also. To compensate for that, the application DRM
application 320 registers itself to receive processor clock data in
the form of periodic CPU ticks (or time units) from the
processor clock 324. This value is available in most operating
systems that could be employed by processing device 304. This
processor clock data may be merely a monotonically-increasing
number that is reset each time the system is restarted. The
processor clock data is periodically (such as each few seconds)
stored as an elapsed processor clock time. Upon each
application restart, the processor clock data will start from zero
and its value gets added to the stored elapsed processor clock
time. While the application is running, the combination of the
elapsed processor clock time and the last saved server time
indicate the current time.
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Appeal2015-005821
Application 13/732,527
Id. (citing Spec. 6). Appellant also cites the definition of "clock" from the
IEEE dictionary:
1 (b) A device that measures and indicates time
1 ( c) A register whose content changes at regular intervals in
such a way as to measure time.
Id. Appellant submits an appropriate definition of "processor clock" is a
device or register associated with a processor whose content changes at
regular intervals in such a way as to measure time. Id. Appellant argues that
a user-selectable or a predetermined offset value is not consonant with the
claimed "processor clock," in light of the Specification or the IEEE
dictionary. Id. at 7.
The Examiner finds that Claim 1 recites" ... the processor clock data"
not "processor clock." Under the broadest reasonable interpretation, "the
processor clock data" is interpreted to be a number, and "the time offset"
disclosed by Parks is a number, thus, it is reasonable to interpret the claim
limitation "the processor clock data" to be "the time offset" as taught by
Parks. Ans. 6.
Appellant replies the time offset is not processor clock data generated
by a processor clock. Reply Br. 3. Rather, Parks' time offset is either a
user-generated value or is a pre-determined value, but neither is generated
by a processor clock. Id.
We agree with Appellant. In view of the foregoing discussion, we
reverse the rejection of Claims 1-15.
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Appeal2015-005821
Application 13/732,527
DECISION
The rejection of Claims 1-15 under 35 U.S.C. § 103(a) is
REVERSED.
REVERSED
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