Ex Parte Sao

Patent Trial and Appeal Board

Jun 23, 2017

13553851 (P.T.A.B. Jun. 23, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/553,851 07/20/2012 Charles SAO 6046-0144PUS1 8735
127226 7590 06/27/2017
BIRCH, STEWART, KOLASCH & BIRCH, LLP
8110 Gatehouse Road
Suite 100 East
Falls Church, VA 22042-1248
EXAMINER
AHMAD, SHAHZEB K
ART UNIT PAPER NUMBER
2838
NOTIFICATION DATE DELIVERY MODE
06/27/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
mailroom @ bskb. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL
AND APPEAL BOARD
Ex parte CHARLES SAO
Appeal 2016-002436
Application 13/553,851
Technology Center 2800
Before JEFFREY T. SMITH, MICHAEL P. COLAIANNI, and
LILAN REN, Administrative Patent Judges.
COLAIANNI, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134 the final rejection of claims
1, 2, 4—8, 10-12, 18, and 20. We have jurisdiction over the appeal pursuant
to 35 U.S.C. § 6(b).
We AFFIRM.
Appeal 2016-002436
Application 13/553,851
Appellant’s invention is directed to a method for supplying electric
power to a load through a filter bus using an arrangement, in which the
arrangement comprises at least two voltage source converters connected in
parallel to said filter bus through an inductor each configured to share the
load (Spec. 1:11—16).
Claim 1 is illustrative:
1. An arrangement for supplying electric power to a load
through a filter bus, the arrangement comprising
at least two Voltage Source Converters connected in
parallel to said filter bus through an inductor each and
configured to share said load, and
for each said converter, a control unit configured to
regulate the voltage of the filter bus while maintaining dynamic
control of the current from the converter, each said control unit
is configured to
produce two perpendicularly-intersecting filter bus
voltage vectors (v/v, v/y) from said filter bus voltage (v/),
produce a filter bus voltage reference vector (v%, v/r) for
each of said two filter bus voltage vectors,
sum each said filter bus voltage vector (vjx, vjy) and the
filter bus voltage reference vector (v%, v*jy) associated
therewith,
include a regulator to receive a sum of each said filter bus
voltage vector (v/x, v /,) and the filter bus voltage reference
vector {v*fx, v*/y) associated therewith, so as to produce a
current reference vector (iVaiim, iky-unim) for each said filter
bus voltage vector (v/v, vjy), and
involve current control in the control of said converter
based on said current reference vectors for obtaining two
vectors (A, iky) of the current from said converter
perpendicularly-intersecting each other,
wherein said control unit is further configured to multiply
each said current vector (zA, hy) or current reference vector (i A-
Un\im, i*kxUrAim? i*kx, i%) with a droop coefficient (Dpn) common to
all said current vectors or current reference vectors as a
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Application 13/553,851
multiplication result and subtract the multiplication result from
the respective filter bus voltage reference vector (v*/x, v*/j), and
wherein said control unit is further configured to sum an
output signal from said regulator and a feed-forward signal
representing a load current so as to produce said current
reference vector for each said filter bus voltage vector (v/v, vjy).
Appellant appeals the following rejections:
1. Claims 1, 2, 4—8, 10-12, 18, and 20 are rejected under 35 U.S.C.
§ 112, first paragraph, as lacking enablement.
2. Claims 1, 2, 4, 5, 7, 8, 10-12, 18, and 20 are rejected under 35 U.S.C.
§ 103(a) as unpatentable over Kelly (GB 2 429 306 A, pub. Feb. 21,
2007) in view of Moran (US 5,355,025, iss. Oct. 11, 1994).
3. Claim 6 is rejected under 35 U.S.C. § 103(a) as unpatentable over
Kelly in view of Moran, and Divan (US 5,596,492, iss. Jan. 21, 1997).
FINDINGS OF FACT & ANALYSIS
REJECTION (1): 35 U.S.C. § 112,11
The Examiner concludes that claim 1 lacks enablement because the
claims and Specification fail to show or explain how the two
perpendicularly-intersecting filter bus voltage vectors (v/x or v/y) values are
produced or created by the control unit (Final Act. 4). The Examiner finds
that the Specification merely states that there is a “first means” but does not
specify what constitutes a first means or explain how the first means is
configured to produce the perpendicularly intersecting vectors. Id. The
Examiner finds that Appellant’s reliance on Figure 4 for enablement is
insufficient because Figure 4 merely shows the first means as component 11
which is only an arrow flowing out of component 23 in the figure (Final Act.
4). The Examiner further finds that “each said control unit is configured to .
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Application 13/553,851
. . produce a filter bus voltage reference vector (v*fx, v*fy) for each of said
filter bus voltage vectors” in claim 1 is not enabled because the claims and
Specification fail to teach how the control unit produces set vectors and
through what means (Final Act. 4). The Examiner finds that the
Specification states that a “second means” and an operator sets the values
but provides no guidance on what the values are or how they are set (Final
Act. 4—5). The Examiner finds that the reference values may be used as
settings to be achieved but may also be threshold control signals and the
Specification provides no guidance on how to set such threshold values
(Final Act. 5).
Appellant argues that Kelly, as prior art, show the production of two
perpendicularly-intersecting voltage vectors from a voltage is known and
would not have involved undue experimentation (Br. 7). Appellant contends
that claim 7’s recitation of a control unit configured to produce two
perpendicularly-intersecting filter bus voltage vectors is a well-known
mathematical transformation between two coordinate systems known as a
Park’s transformation (Br. 8). Appellant contends that the reference
authored by S.A. Soliman et al. evinces that Park’s transformations are well
known to a person skilled in the art (Br. 8). Appellant argues that because
producing perpendicularly-intersecting vectors is a well-known
mathematical transformation, no undue experimentation would have been
required to make or use the claimed invention. Id. Regarding the claim 1
and claim 7 limitation that the control unit is configured to produce a filter
bus voltage reference vector for each of said two filter bus voltage vectors,
Appellant argues that such limitation merely provide suitable target values
for the x and y components of the filter bus voltage in the d-q reference
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Application 13/553,851
frame (Br. 9). Appellant contends that because the converters are not
connected to the bulk grid and consequently use a locally generated
reference frame, a person of ordinary skill in the art would have known that
the components can have any values as long as the magnitude of the voltage
remains within safe operating limits of the converter. Id. Appellant argues
that a person of ordinary skill would have been able to determine suitable
values for the filter bus voltage reference vector with the values being
explicitly disclosed in the Specification. Id.
The preponderance of the evidence weighs in favor of the Examiner’s
conclusion that the claims lack enablement. The Examiner provides a
thorough analysis of the factors set-forth in In re Wands, 858 F.2d 731, 737
(Fed. Cir. 1988) that may be considered when assessing whether a claim is
enabled (Ans. 4—8). We agree with the Examiner’s Wands factor analysis,
which was not responded to by Appellant. We add the following primarily
for emphasis. The Examiner finds that the Specification describes the
control unit has a “means” within the control unit that creates the
perpendicularly-intersecting vectors (Ans. 8). We understand the Examiner
to find that the claims, as read in light of the Specification, do not describe
the structure of the control unit recited in claims 1 and 7 that enables it to
create the perpendicularly-intersecting vectors. The Examiner finds the
breadth of the claims is such that undue experimentation would have been
required to practice the claimed invention.
With regard to Appellant’s argument that Kelly and Soliman et al.
provide evidence that the technique used to transform data is well known,
the Examiner finds that to perform such Park’s transformations, reasoning
and information are essential components and the present Specification fails
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Application 13/553,851
to provide the information necessary to enable one of ordinary skill to make
and use the claimed invention. In other words, the Examiner finds that even
if the transformation technique is well-known, the information necessary to
perform the transformation is not necessarily known. Appellant does not
dispute these findings of the Examiner.
On this record, we find that Appellant has not shown reversible error
in the Examiner’s enablement analysis as described with regard to the
Wands factors. We affirm the 35 U.S.C. § 112,11 as lacking enablement.
REJECTION (2): 35 U.S.C. § 103
Appellant argues the following groups of claims: (1) claims 1 and 7,
(2) claims 2 and 8, (3) claims 4, 10, and 18, and (4), claims 5, 11, and 20
(Br. 10—17). We select the following claims as representative of its
particular grouping: (1) claim 1; (2) claim 2; (3) claim 4, and (4) claim 5.
Appellant relies on arguments made regarding claim 7 in arguing claim 12
(Br. 17). Accordingly, claim 12 will stand or fall with our analysis of the
rejection of claim 1.
CLAIM 1
Appellant argues that claim 1 requires that the two filter bus voltage
vectors are perpendicularly-intersecting filter bus voltage vectors, which
requires that the filter bus voltage reference vectors and the two current
reference vectors are also for the two perpendicularly-intersecting filter bus
voltage vectors (Br. 12). Appellant contends that even though Kelly teaches
two voltage reference vectors and two current reference vectors for two
perpendicularly-intersecting voltage vectors, the feed-forwarding signal
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Application 13/553,851
(isa*, isb*, isc*) of Moran are not for any two perpendicularly intersecting
voltage vectors (Br. 12). Appellant contends that the three current
references provided in Moran’s Figure 22 are not for each of the two
perpendicularly-intersecting voltage vectors such that one of skill in the art
would not have been motivated to modify Kelly to sum the two current
reference vectors (Idtgt, Iqtgt) with the three feed-forwarding signals of Moran
(Br. 13).
Appellant’s arguments are not persuasive because the Examiner’s
rejection is based upon Kelly teaching the two perpendicularly-intersecting
voltage vectors (Final Act. 6). Appellant’s argument that Moran does not
teach using the feed-forward signals on any perpendicularly-intersecting
voltage vectors, fails to address the Examiner’s position that based upon the
teachings of Kelly and Moran, as a whole, it would have been obvious to use
Moran’s current feedback path of the load in order to provide a better control
scheme allowing for less power loss and better efficiency (Final Act. 7). In
other words, the Examiner finds that Kelly teaches all the limitations of
claim 1, except for the requirement that the control unit is further configured
to sum an output signal from said regulator and a feed-forward signal
representing load current so as to produce said current reference vector for
each said filter bus voltage vector (Final Act. 5—7). The Examiner finds that
Moran teaches the claimed control arrangement that includes adding two
values and then using those values to produce a set of current vectors that is
being taught by Moran (Final Act. 7; Ans. 10). The Examiner is not
proposing to bodily incorporate Moran’s controller into Kelly’s system, but
rather modifying Kelly’s control arrangement to use Moran’s control
arrangement in order to reduce power loss and provide better efficiency
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Application 13/553,851
(Ans. 10). Appellant’s argument does not establish reversible error with the
Examiner’s rejection.
CLAIM 2
Appellant argues that Kelly nowhere discloses two limited current
reference vectors are respectively obtained by respectively limiting the
magnitude of the two current reference vectors (Br. 14). Appellant contends
that Kelly obtains only one limited current reference vector by combining
the two current reference vectors, not by limiting the magnitude of only one
of the two current reference vectors. Id.
The Examiner finds that claim 2 can be read as requiring that each
current reference vector is combined to produce a single limited current
reference vector (Ans. 11). Based upon this claim construction, the
Examiner finds that Kelly discloses the subject matter of claim 2. Id.
Claim 2 recites “wherein each said control unit for the respective said
converter further comprises a current limiter configured to receive current
reference vector {i*kx-un\im, fky-uniim) for each said filter bus voltage vector
from said regulator and to limit the magnitude of each said current reference
vector to be a limited current reference vector {fkx, /%■)•” (emphasis added).
The plain meaning of claim 2 is that each current reference vector, which
includes two vectors {i*kx-un\im, fky-un\\m), are limited for each vector to yield
limited current reference vector for each current reference vector, which also
includes two vectors {fkx, i*hf). The Examiner’s finding that claim 2 includes
Kelly’s combining the two current reference vectors into a single limited
current reference vector appears to be contrary to the plain meaning of the
claim.
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Application 13/553,851
Based upon the Examiner’s claim construction, we are constrained to
reverse the Examiner’s § 103 rejection of claims 2 and 8.
CLAIM 4
Appellant argues that the Examiner relies on Kelly’s Idtgt and Iqtgt as
the current reference vectors and IXd and Ixq as the two vectors of the current
(Br. 15). Appellant argues that IXd and Ixq are not obtained based on the two
current reference vectors Idtgt and Iqtgt as required by claim 4 (Br. 15—16).
The Examiner finds that “based on” in claim 4 includes an
arrangement where the current control “in any way affects the current
vector” (Ans. 12). The Examiner finds that vectors Idtgt and Iqtgt are
combined to form Ixtgt, which is output to control the inverter shown in
Figure 6 and, based on the value returned, the output of the inverter 13 is
determined and then resubmitted into the control flow of Figures 1 to 5. Id.
The Examiner finds that the resubmitting of the values would change the
value of Ix as it would be determined by the Ia, lb, and Ic shown in Figure 6,
which would change the values of IXd and Ixq, which would satisfy the
condition that Ixd and Iqd are based upon the values if Idtgt and Iqtgt. Id.
Appellant does not respond to or otherwise show reversible error with
the Examiner’s prima facie case of obviousness noted above as it is
Appellant’s burden to do. In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011).
On this record, we affirm the Examiner’s rejection of claim 4.
CLAIM 5
Appellant argues that in Kelly components Ixd and Ixq of AC current
signal Ix are obtained based on the current reference vectors Idtgt and Iqtgt
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(App. Br. 16—17). Appellant argues that IXd and Ixq are obtained from
Kelly’s RT-DQ block 53, which resolves Ix into direct component Ixd and Ixq
and has nothing to do with the alternating target current signal Ixtgt as shown
in Figure 3 of Kelly (App. Br. 17). The Examiner has already addressed
how Kelly teaches that components IXd and Ixq of AC current signal Ix are
obtained based on current reference vectors Idtgt and Idtqt with regard to claim
4. Appellant has not shown the Examiner’s reasoning or findings to
constitute reversible error.
Appellant further argues that Kelly’s IXd and Ixq components are
produced in a d-q frame, not an a-B frame (Br. 17). The Examiner finds and
Appellant does not dispute that Park transformations (i.e., in the d-q frame)
inherently have an a-B frame set within it as that Park transformation
calculation is split into a Clarke transformation (i.e., a-B frame) and one
rotation of phase shift (Ans. 12—13). The Examiner finds that Kelly’s first
calculation that has no rotation and no phase shift can be seen as employing
an a-B frame (Br. 13). Appellant does not show reversible error with any of
the Examiner’s findings regarding Kelly implicitly teaching an a-B frame.
On this record, we affirm the Examiner’s § 103(a) rejection of
claim 5.
REJECTION (2): CLAIM 6
Appellant argues that neither Kelly, Morgan, nor Divan teach or
suggest that the filter (42 and 43) will be located when applied to Kelly’s
circuit (Br. 18). Appellant argues that the combined teachings of Kelly,
Morgan and Divan fail to teach that the filter (42 and 43) is used for
smoothing out the filter bus voltage vectors (v^, vry) before summing said
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Application 13/553,851
filter bus voltage vector (v&, vry) to said filter bus voltage reference (v*rx,
v*iy) associated therewith (Br. 18).
The Examiner finds that Divan would have suggested that in the
placement and sequence of creating new voltage vectors it is reasonable to
find that a filter can be placed before the summing occurs (Ans. 14). The
Examiner also finds that a filter is a simple circuit component that helps
filter out unwanted noise or static and is known in the art to be placed
anywhere within the circuit (Br. 14). Appellant does not dispute these
findings of the Examiner.
On this record, we affirm the Examiner’s § 103 rejection of claim 6
over Kelly in view of Morgan and Divan.
DECISION
The Examiner’s decision is affirmed.
The rejection claims 1, 2, 4—8, 10-12, 18, and 20 under 35 U.S.C. §
112, first paragraph, as lacking enablement is affirmed.
The rejection under 35 U.S.C. § 103(a) of claims 1, 4—7, 10—12, 18,
and 20 are affirmed.
The rejection under 35 U.S.C. § 103(a) of claims 2 and 8 is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
ORDER
AFFIRMED
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