Ex Parte SankaranDownload PDFPatent Trial and Appeal BoardOct 31, 201412131563 (P.T.A.B. Oct. 31, 2014) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte JAGADEESH SANKARAN __________ Appeal 2012-007332 Application 12/131,563 Technology Center 2800 ____________ Before ADRIENE LEPIANE HANLON, CHARLES F. WARREN, and KRISTINA M. KALAN, Administrative Patent Judges. KALAN, Administrative Patent Judge. DECISION ON APPEAL Appeal 2012-007332 Application 12/131,563 2 Appellant1 appeals under 35 U.S.C. § 134(a) from the decision of the Primary Examiner finally rejecting claims 1–7. We have jurisdiction over the appeal pursuant to 35 U.S.C. § 6(b). We AFFIRM. STATEMENT OF THE CASE Appellant’s invention is directed to “performance benchmarking of multiprocessor video codec’s [sic] employed in image transmission systems such as video conferencing and in video compression.” Spec. 1:7–10. The invention “implements a benchmark counter in each processor.” Id. at 4:7– 8. Appellant summarizes that because all processing elements run synchronous to corresponding clocks, “measuring co-processor performance really amounts to just counting the number of clock ticks consumed by the processor. A start command resets the benchmark counter, which then starts incrementing with every subsequent clock tick. The benchmark counter stops incrementing when it sees an end command.” Id. at 4:8–15. Claim 1 is illustrative: 1. An execution benchmarking apparatus for a multiprocessor system comprising: a plurality of data processing units, each data processing unit operable to perform data processing operations synchronously with a corresponding clock, each data processing unit including a benchmark counter, said benchmark counter operable to count clock cycles of the corresponding digital processing unit when said corresponding data processing unit is operating, each data processing unit operable to begin data processing operations on said data processing unit and reset said benchmark counter upon detection of a start command, 1 Appellant identifies the real party in interest as Texas Instruments Incorporated. Appeal Brief filed October 12, 2011 (“App. Br.”) at 3. Appeal 2012-007332 Application 12/131,563 3 increment said corresponding benchmark counter synchronously with each clock cycle of said corresponding clock following said detection of said start command, stopping data processing operations on said data processing unit upon detection of a stop command, not incrementing said benchmark counter synchronously with each clock cycle of said corresponding clock following said detection of said stop command, said benchmark counter thereby storing a number of clocks consumed by said data processing unit from said start command to said stop command, and permitting said corresponding benchmark counter to be read when stopped. App. Br. 14, Claims App’x. The Examiner maintains,2 and Appellant appeals, the rejection of claims 1–7 under 35 U.S.C. § 102(b) as anticipated by Chapple.3 We have considered the claim groupings, and to the extent that the claims on appeal are argued separately, we will address them separately consistent with 37 C.F.R. § 41.37(c)(1)(vii). The issues on appeal are resolved based upon the correct interpretation of the claims as will become evident from our discussion that follows. We affirm substantially for the reasons provided by Examiner in the Answer. We add the following. ANALYSIS Argument 1 Appellant argues that Chapple does not disclose the limitation of “begin data processing operations on said data processing unit and reset said benchmark counter upon detection of a start command” of Claim 1 or “starting data processing operations on said data processor synchronously 2 Examiner’s Answer mailed January 31, 2012 (“Ans.”) at 4–6. 3 US Patent No. 6,519,310 B2, issued February 11, 2003. Appeal 2012-007332 Application 12/131,563 4 with a corresponding clock and resetting said corresponding benchmark counter” of Claim 4. App. Br. 9. Specifically, Appellant argues that Chapple teaches resetting the benchmark counter, but does not teach beginning data processing operations, or starting data processing operations on the data processor synchronous with the clock. Id. The Examiner finds that Chapple discloses a benchmark counter (performance counter), a plurality of data processing units (or counter blocks) each performing data processing operations comprising not only counting events, but also providing other data, with synchronization. Ans. 7. The Examiner further finds that because “data collection is part of the data processing operation, counting event data is a data processing operation as it collects data to determine data processing performance.” Id. The Examiner notes that Chapple discloses “if the command is a Restart command, the counter resets and then starts counting again. This is essentially a Reset command and a Start command combined into a single command.” Id. Finally, the Examiner finds that at Chapple’s Restart command, data processing operation (or counting events) begins synchronously with the clock in each of the data processing units. Id. at 7–8. Appellant challenges the Examiner’s interpretation of the data processing operations and the counting of claims 1 and 4 as the same. Reply Brief filed March 30, 2012 (“Reply Br.”) 2. Appellant further argues that the language of claims 1 and 4 requires that the data processor include other parts beyond the benchmark counter, and requires counting of the benchmark counter to be separate from the operation of the data processing unit, namely, “separate recitation implies separate parts and separate operations.” Id. Appeal 2012-007332 Application 12/131,563 5 The Examiner correctly finds, and Appellant has not persuasively refuted, that a “counting event is a data processing operation as it collects data to determine data processing performance.” Ans. 7. The Examiner also correctly finds that the combination of a Reset command and a Start command, as explained by Chapple, anticipates the subject limitations of Appellant’s claims 1 and 4. Appellant has not provided any persuasive reasoning why the Restart command does not anticipate the “begin” or “starting,” and the “reset” or “resetting” of the limitations of the disputed claims. In the case of claim 1 in particular, where the claim language requires only that the data processing unit be “operable to” begin data processing operations and reset said benchmark counter, Appellant has not shown that Chapple’s disclosure is not capable of the same operations. Argument 2 Appellant argues that Chapple does not disclose the limitation of “increment said corresponding benchmark counter synchronously with each clock cycle of said corresponding clock following said detection of said start command” of Claim 1 or “following said detection of said start command incrementing said corresponding benchmark counter synchronously with each clock cycle of said corresponding clock” of Claim 4. App. Br. 9–10. Specifically, Appellant argues that “Chapple regards events and clock ticks as separate entities.” Id. at 10. The Examiner finds that Chapple discloses counting two different types of events, namely, single occurrence type events and duration type events. Ans. 8. An example of a single occurrence type event is shown in Figure 4, “wherein single events occupy one ticking clock cycle.” Id. An example of duration type events, on the other hand, is given in Chapple Appeal 2012-007332 Application 12/131,563 6 4:63–66 (“all duration type events toggle every counter block clock tick that the event is true”) and illustrated in Examiner’s schematic representation. Id. at 9. The Examiner finds that the latter anticipates the disputed language of claims 1 and 4. Id. at 9. Appellant argues that the subject language of claims 1 and 4 “makes incrementing the benchmark counter unconditional and independent of any status of a duration type event.” Reply Br. 3. We are not persuaded. The language of claims 1 and 4 is not so restrictive as to discredit the Examiner’s finding that Chapple’s counting during a duration type event anticipates the limitations of claims 1 and 4. Appellant’s arguments that benchmark counter incrementing is “unconditional and independent of any status of a duration type event” is based on limitations not found in the claims. Again, in the case of claim 1, where the claim language requires only that the data processing unit be “operable to” increment said corresponding benchmark counter synchronously with each clock cycle of said corresponding clock following said detection of said start command, Appellant has not shown that Chapple’s disclosure is not capable of the same operations. Examiner has made those findings in the figure, Appellant has not shown any error. Argument 3 Appellant argues that Chapple does not disclose the limitation of “stopping data processing operations on said data processing unit upon detection of a stop command, not incrementing said benchmark counter synchronously with each clock cycle of said corresponding clock following said detection of said stop command” of Claim 1 or “upon detection of a stop command at said data processor stopping data processing operations on said data processing unit; following said detection of said start command Appeal 2012-007332 Application 12/131,563 7 stopping incrementing said corresponding benchmark counter” of Claim 4. App. Br. 11. Appellant further argues that the two actions begun by detection of the stop command are (1) stopping data processing operations on the data processor synchronous with the clock, and (2) stopping incrementing the benchmark counter, and that while Chapple teaches stopping the counter, it fails to teach stopping data processing operations. Id. at 11–12. The Examiner finds that Chapple discloses that “if the command is a Stop command, then the associated counter does not count.” Ans. 10; Chapple 4:59–61, 6:35–38. The Examiner reasons that “counting events is a data processing operation. As such, stopping the counter, stops counting, or stops data processing operations.” Id. Appellant provides no countervailing arguments in the Reply Brief. As we have stated above, the Examiner correctly finds that the counting event is a data processing operation. Thus, we are persuaded that the Examiner’s finding of a Stop command that stops data processing operations is reasonably supported by the record. Argument 4 Appellant argues that Chapple does not disclose the limitations of “said counter is operable to generate an interrupt following detection of a stop command” of claim 2, “in a first mode whereby said counter generates an interrupt following detection of a stop command” of claim 3, “generating an interrupt upon detection of said stop command” of claim 6, or “in a first mode generating an interrupt following detection of said stop command” of claim 7. App. Br. 12. The Examiner finds that Chapple discloses generating interrupt from one of the counters following the detection of the stop command, relying on Appeal 2012-007332 Application 12/131,563 8 Figure 1 (Command trigger 102 → stop command → compare 108 → threshold event true → interrupt), wherein the stop command stops counting events. Ans. 10–11. Appellant responds that the Examiner’s interpretation requires inclusion of two additional occurrences (compare 108 → threshold event true) following the stop command before an interrupt is generated. Reply Br. 3–4. We are not persuaded. The claims do not require that no intermediate steps be present between the stop command and the interrupt, and the Appellant does not present any additional persuasive arguments to refute the Examiner’s finding. Thus, the Examiner reasonably found that the stop command leading to an interrupt is anticipated by Chapple. Argument 5 Finally, Appellant argues that Chapple does not disclose the limitation of “operating said data processor on a benchmark program upon detection of said start command” of claim 5. App. Br. 13. The Examiner finds that Chapple discloses operating the data processor on a benchmark program upon detection of a start command, and halting operation of the data processor upon detection of the stop command, where each of the data processing units (counter blocks) are programmed to start counting the cache hit events. Ans. 12. Based on the Examiner’s finding that performance counters are benchmark counters, and incorporating our reasoning from above regarding Chapple’s disclosure of start commands, we are persuaded that the Examiner has made a prima facie case, which Appellant has not refuted. Appeal 2012-007332 Application 12/131,563 9 ORDER The decision of the Examiner is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. §1.136(a). AFFIRMED kmm Copy with citationCopy as parenthetical citation