Ex Parte Sandy et al

Board of Patent Appeals and Interferences

Feb 23, 2010

10996890 (B.P.A.I. Feb. 23, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte DOUGLAS L. SANDY, JEFFREY M. HARRIS,
and ROBERT C. TUFFORD
____________________

Appeal 2009-004422
Application 10/996,890
Technology Center 2100
____________________

Decided: February 23, 2010
____________________

Before LEE E. BARRETT, JEAN R. HOMERE, and THU A. DANG,
Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2009-004422
Application 10/996,890

I. STATEMENT OF CASE
Appellants appeal the Examiner’s final rejection of claims 1-16 under
35 U.S.C. § 134(a). Claims 17-23 are canceled. We have jurisdiction under
35 U.S.C. § 6(b).
We affirm.

A. INVENTION
According to Appellants, the invention relates to a method of
transporting a Peripheral Component Interconnect (PCI) Express packet over
a VERSAmodule Eurocard (VMEbus) network (Spec. 15, ll. 6-7).

B. ILLUSTRATIVE CLAIM
Claim 1 is exemplary and reproduced below:

1. In a computer network, a method of transporting a
PCI Express packet from an initiator PCI Express domain over
a VMEbus network to a receiver PCI Express domain,
comprising:

the initiator PCI Express domain creating the PCI
Express packet;

reading a first PCI Express destination address of the PCI
Express packet;

mapping the first PCI Express destination address to a
receiver PCI Express domain VMEbus address;

encapsulating the PCI Express packet in a data field of a
VMEbus write transaction; and

communicating the VMEbus write transaction to the
receiver PCI Express domain over the VMEbus network.
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C. REJECTION
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:

Tal US 6,662,254 B1 Dec. 9, 2003

Claims 1-16 stand rejected under 35 U.S .C. § 103(a) as being
unpatentable over the combination of Appellants’ Admitted Prior Art
(“AAPA”) and Tal.

II. ISSUES
Have Appellants shown the Examiner erred in concluding that AAPA
in view of Tal would have taught or suggested:
1) “encapsulating the PCI Express packet in a data field of a
VMEbus write transaction” (claim 1); and
2) “mapping the first PCI Express destination address to a receiver
PCI Express domain VMEbus address” (claim 1)?

III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
AAPA
1) AAPA discloses a system whereby a PCI Express domain
translates data to a VMEbus protocol and the translated data is transmitted
over a VMEbus network to another PCI Express domain (Spec. 1, ll. 7-21).
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Tal
2) Tal discloses a PCI compatible system (col. 4, ll. 61-64), which
includes I/O modules and a router module providing “non-IP traffic to IP
networks” (col. 7, ll. 27-29).
3) When an I/O module receives non-IP data, it adds IP transport
headers as defined for that non-IP data channel and then encapsulates the
resulting IP datagram within an Ethernet frame having a destination Media
Access Control (“MAC”) address of the router module (col. 8, ll. 23-32).
4) The Ethernet frame is sent by the I/O module to the router,
which determines a destination MAC address corresponding to the IP
datagram’s destination IP address and performs switching according to that
destination MAC address (col. 8, ll. 32-36).

IV. PRINCIPLES OF LAW
Claim Interpretation
The claims measure the invention. See SRI Int’l v. Matsushita Elec.
Corp., 775 F.2d 1107, 1121 (Fed. Cir. 1985) (en banc). “[T]he PTO gives
claims their ‘broadest reasonable interpretation.’” In re Bigio, 381 F.3d
1320, 1324 (Fed. Cir. 2004) (quoting In re Hyatt, 211 F.3d 1367, 1372 (Fed.
Cir. 2000)). “Moreover, limitations are not to be read into the claims from
the specification.” In re Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993)
(citing In re Zletz, 893 F.2d 319, 321 (Fed. Cir. 1989)).
35 U.S.C. § 103(a)
Section 103 forbids issuance of a patent when “the
differences between the subject matter sought to be patented
and the prior art are such that the subject matter as a whole
would have been obvious at the time the invention was made to
a person having ordinary skill in the art to which said subject
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matter pertains.”

KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). In KSR, the
Supreme Court emphasized “the need for caution in granting a patent based
on the combination of elements found in the prior art,” and discussed
circumstances in which a patent might be determined to be obvious. Id. at
415 (citing Graham v. John Deere Co., 383 U.S. 1, 12 (1966)). The Court
reaffirmed principles based on its precedent that “[t]he combination of
familiar elements according to known methods is likely to be obvious when
it does no more than yield predictable results.” Id. at 416.
In affirming a determination of obviousness, the Federal Circuit has
relied, in part, on an applicant’s failure to present evidence that the proposed
combination of teachings was “uniquely challenging or difficult for one of
ordinary skill in the art” or “represented an unobvious step over the prior
art.” Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed.
Cir. 2007) (citing KSR, 550 U.S. at 418-19).
One cannot show nonobviousness by attacking references individually
where the rejections are based on combinations of references. In re Merck
& Co., Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986).

V. ANALYSIS
As to independent claim 1, Appellants argue that AAPA merely
shows prior art “data must be translated (not encapsulated as claimed by
Appellants) between PCI Express and VMEbus protocols at the interface of
the PCI Express card and the VMEbus network” (App. Br. 6). Appellants
further argue that Tal also “does not teach the encapsulating the PCI Express
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packet in a data field of a VMEbus write transaction,” but rather “includes
its necessary step of encapsulating into an IP packet” (App. Br. 7).
The Examiner responds that “the proposed combination was made to
provide a teaching to allow for the system of AAPA to be able to transmit
PCI Express packets between two PCI Express domains over a VMEbus
without requiring the PCI Express packets to be translated into a VMEbus
transaction” (Ans. 7-8). The Examiner explains:
Tal was used in the rejection for the purpose of teaching
mapping a PCI packet destination address to a receiver PCI
device, encapsulating the PCI packet into an non-PCI
transaction (e.g., a VMEbus transaction in the proposed
combination), and transmitting the encapsulated PCI packet to
the receiver PCI device according to the destination address.

(Ans. 8; citations omitted).
Thus, an issue we address on appeal is whether the Examiner erred in
finding that the combination of AAPA and Tal would have taught or
suggested “encapsulating the PCI Express packet in a data field of a
VMEbus write transaction” (claim 1).
We begin our analysis by giving the claims their broadest reasonable
interpretation. See In re Bigio, 381 F.3d at 1324. Furthermore, our analysis
will not read limitations into the claims from the specification. See In re
Van Geuns, 988 F.2d at 1184.
Claim 1 simply does not place any limitation on what “data field”
means, includes, or represents. We interpret “data field” as reading on any
portion of the recited “write transaction.” We therefore interpret the recited
“encapsulating the PCI Express packet in a data field of a VMEbus write
transaction” as reading on the encapsulation of a PCI Express packet within
any portion of a VMEbus write transaction.
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AAPA discloses a PCI Express domain that translates data to a
VMEbus protocol and then transmits the translated data over a VMEbus
network (FF 1). An ordinarily skilled artisan would have understood AAPA
as teaching or suggesting PCI Express domains/packets and VMEbus, as
recited in claim 1.
Tal discloses a PCI compatible system having I/O modules and a
router providing “non-IP traffic to IP networks” (FF 2). When an I/O
module receives non-IP data, it adds IP transport headers and encapsulates
the resulting IP datagram within an Ethernet frame having a destination
MAC address of the router (FF 3). The I/O module then sends the Ethernet
frame to the router, which determines a destination MAC address
corresponding to the IP datagram’s destination IP address and then forwards
the Ethernet frame to that destination MAC address (FF 4). In particular,
Tal discloses an encapsulation of PCI data within the transmissions of other
protocols, i.e., within IP and MAC transmissions (FF 3-4).
We find the skilled artisan would have understood the combination of
AAPA in view of Tal as teaching or suggesting an encapsulation of AAPA’s
PCI Express data within a transmission of a non-PCI protocol; e.g., within a
write transaction of AAPA’s VMEbus protocol.
Regarding Appellants’ argument that the “differences between
encapsulating into an IP packet and into a VMEbus write transaction are not
trivial because of the differences between IP and VMEbus protocols” (App.
Br. 7), Appellants present no evidence that encapsulating a PCI Express
packet within a VMEbus write transaction would have been “uniquely
challenging or difficult for one of ordinary skill in the art.” Leapfrog, 485
F.3d at 1162 (citing KSR, 550 U.S. at 418-19). We find that combining the
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PCI Express domains/packets and VMEbus network as taught by AAPA
with Tal’s encapsulation of PCI data within the transmissions of other
protocols, i.e., within IP and MAC transmissions, is no more than a simple
arrangement of old elements, with each performing their ordinary function,
yielding no more than a predictable result. See KSR, 550 U.S. at 417. Thus,
we find this argument unpersuasive.
For the above reasons, Appellants have not shown that the Examiner
erred in finding that the combination of AAPA in view of Tal would have
taught or suggested “encapsulating the PCI Express packet in a data field of
a VMEbus write transaction” (claim 1).
Appellants also argue that “Tal does not disclose mapping of the first
PCI Express destination address to a receiver PCI Express domain VMEbus
address” (App. Br. 7). Stating that the rejection equates the VMEbus of
claim 1 to Tal’s IP network, Appellants further argue that “[a]s is understood
by the Specification and by one of ordinary skill in the art, the receiver PCI
Express domain VMEbus address . . . . includes more data than just the I/O
card identified by the IP address and disclosed by Tal” (App. Br. 7).
As noted above, the Examiner cites to AAPA as teaching the recited
PCI Express domains/packets and VMEbus, but cites to Tal as “mapping a
PCI packet destination address to a receiver PCI device” for transmission via
a “non-PCI transaction (e.g., a VMEbus transaction in the proposed
combination)” (Ans. 8; citation omitted).
Thus, another issue we address on appeal is whether the Examiner
erred in finding that the combination of AAPA in view of Tal would have
taught or suggested “mapping the first PCI Express destination address to a
receiver PCI Express domain VMEbus address” (claim 1).
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Regarding Appellants’ argument that Tal does not disclose the recited
“mapping of the first PCI Express destination address to a receiver PCI
Express domain VMEbus address,” the Examiner applies both AAPA and
Tal (i.e., not only Tal) to this limitation. More particularly, the Examiner
finds that an ordinarily skilled artisan would have mapped addresses of
AAPA’s PCI Express packets to addresses of AAPA’s VMEbus network
(i.e., mapped PCI addresses to VMEbus addresses); and done so in view of
Tal’s teaching that PCI addresses can be mapped to non-PCI addresses in
order to transmit PCI packets over non-PCI networks. As Appellants’
argument addresses only Tal and not the proposed combination of AAPA
and Tal, we find their argument unpersuasive. See In re Merck, 800 F.2d at
1097.
Regarding Appellants’ argument that a “PCI Express domain
VMEbus address includes more data than just the I/O card identified by the
IP address” disclosed by Tal (App. Br. 7), Appellants appear to assert that it
would have been difficult to map PCI addresses to VMEbus addresses (or at
least more difficult than mapping PCI addresses to IP addresses). However,
Appellants present no evidence that (nor even an explanation why)
differences between PCI Express packet addresses and VMEbus addresses
would have made the mapping of PCI Express packet addresses to VMEbus
addresses, as claimed, “uniquely challenging or difficult for one of ordinary
skill in the art.” Leapfrog, 485 F.3d at 1162 (citing KSR, 550 U.S. at 418-
19). Thus, we also find this argument unpersuasive.
For the above reasons, Appellants have not shown that the Examiner
erred in finding that the combination of AAPA and Tal would have taught or
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suggested “mapping the first PCI Express destination address to a receiver
PCI Express domain VMEbus address” (claim 1).
Accordingly, Appellants have not shown the Examiner erred in
rejecting claim 1. We therefore affirm the rejection of claim 1 under 35
U.S.C. § 103(a) as being unpatentable over the combination of AAPA and
Tal.
As Appellants do not provide separate arguments for independent
claims 8, 10, 13, and 15, those claims, as well as claims 2-7, 9, 11, 12, 14,
and 16 depending from claims 1, 8, 10, 13, 15, fall with representative claim
1. See 37 C.F.R. § 41.37(c)(1)(vii). We therefore also affirm the rejection
of claims 2-16 under 35 U.S.C. § 103(a) as being unpatentable over the
combination of AAPA and Tal.

VI. CONCLUSIONS
Appellants have not shown that the Examiner erred in finding that
claims 1-16 are unpatentable over the combination of AAPA and Tal.

VII. DECISION
The Examiner’s decision rejecting claims 1-16 under 35 U.S.C.
§ 103(a) is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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P.O. BOX 828
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