Ex Parte Sakanobe et al

Patent Trial and Appeal Board

May 26, 2016

13058691 (P.T.A.B. May. 26, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/058,691 02/11/2011
21839 7590 05/31/2016
BUCHANAN, INGERSOLL & ROONEY PC
POST OFFICE BOX 1404
ALEXANDRIA, VA 22313-1404
FIRST NAMED INVENTOR
Kazunori Sakanobe
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
1033413-000106 3083
EXAMINER
THOMAS, LUCY M
ART UNIT PAPER NUMBER
2836
NOTIFICATION DATE DELIVERY MODE
05/31/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ADIPDOC 1@BIPC.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KAZUNORI SAKANOBE, KO I CHI ARISA WA,
FUTOSHI OKAW A, and MASATO HAND A 1
Appeal 2014-006311
Application 13/058,691
Technology Center 2800
Before KRISTEN L. DROESCH, TERRENCE W. McMILLIN, and
MATTHEW J. McNEILL, Administrative Patent Judges.
McMILLIN, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision2 on appeal under 35 U.S.C. § 134(a) of the final
rejection of claims 1-5 and 7-16. 3 Final Act. 1. We have jurisdiction under
35 U.S.C. § 6(b).
We affirm.
1 According to Appellants, the real party in interest is Mitsubishi Electric
Corporation. App. Br. 2.
2 Our decision refers to the Final Office Action mailed July 19, 2013 ("Final
Act."); Appellant's Appeal Brief filed December 16, 2013 ("App. Br."); the
Examiner's Answer mailed March 6, 2014 ("Ans."); Appellant's Reply Brief
filed May 5, 2014 ("Reply Br."); and the Specification filed February 11,
2011 ("Spec.").
3 Claims 1-19 are pending; claims 6 and 17-19 are objected to. Final Act. 1.
Appeal 2014-006311
Application 13/058,691
REJECTIONS ON APPEAL
Claims 12 and 13 stand rejected under 35 U.S.C. §102(b) as being
anticipated by Iimura et al. (US 7,609,498 B2, issued Oct. 27, 2009)
("Iimura"). Final Act. 2.
Claims 1, 2, 4, 5, 7, 9, 14, and 16 stand rejected under 35 U.S.C.
§ 103 (a) as being unpatentable over Iimura and Tsuchida et al. (US
5,936,288, issued Aug. 10, 1999) ("Tsuchida"). Final Act. 3.
Claims 3 and 15 stand rejected under 35 U.S.C. §103(a) as being
unpatentable over Iimura and Shimizu et al. (US 7 ,481,885 B2, issued Jan.
27, 2009) ("Shimizu"). Final Act. 8.
Claims 8, 10, and 11 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Iimura, Tsuchida, and Kato et al. (US 2003/0117753 Al,
published June 26, 2003) ("Kato"). Final Act. 10.
THE CLAIMED INVENTION
According to Appellants' Specification, "[t]he present invention
relates to an overcurrent detection circuit for preventing an electric current
flowing through an inverter from becoming excessive, an inverter, a
compressor, and an air-conditioning machine provided therewith, and to an
adjusting method for adjusting the overcurrent detection circuit." Spec. 1.
Independent claims 1--4 are directed to an overcurrent detection circuit and
independent claims 12 and 13 are directed to a method. Claims Appendix
1--4, 6-7. Claim 1 recites:
1. An overcurrent detection circuit comprising:
a current detection device connected between a direct-
current power source and an inverter in series therewith, for
detecting an electric current flowing through the inverter;
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Appeal 2014-006311
Application 13/058,691
an overcurrent level generation device for generating an
abnormality judgment reference value;
an overcurrent detection device for generating an
interruption signal to the inverter on the basis of an output of
the current detection device and the abnormality judgment
reference value; and
an adjusting apparatus for correcting the abnormality
judgment reference value of the overcurrent level generation
device on the basis of the output at a time when a constant
electric current is applied to the current detection device,
wherein the overcurrent level generation device includes
one or a plurality of resistance value adjusting sections having a
fixed resistor and a zener diode connected to the fixed resistor
in parallel therewith, and generates the abnormality judgment
reference value in correspondence to a resistance value of the
resistance value adjusting section, and
wherein the adjusting apparatus performs a zapping
operation by means of applying a reverse-bias to the zener
diode, and corrects the abnormality judgment reference value.
Claims Appendix 1-2.
ANALYSIS
We have reviewed the rejections of claims 1-5 and 7-16 in light of
Appellants' arguments presented in the Appeal Brief and Reply Brief. We
are not persuaded that Appellants identify reversible error. We agree with
and adopt the Examiner's findings, reasoning, and conclusions as set forth in
the Non-Final Office Action (Non-Final Act. 2-13) and the Examiner's
Answer (Ans. 2-9). We highlight the following for emphasis.
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Appeal 2014-006311
Application 13/058,691
Appellants argue that Iimura fails to disclose, teach, or suggest
adjustment of the abnormality reference value on the basis of the detected
output of a current detection device when a predetermined or constant
electric current is applied to the current detection device as recited in
independent claims 1-4, 12, and 13. App. Br. 13-21; Reply Br. 2-8. The
Examiner responds:
The voltage dividers Rl, R2 ([Iimura] Figures 1-4) are
connected across the current detection device Rs, and by
varying the resistor divider ratio at the node between R 1, R2 by
adjusting the value of the external resistor R3, Iimura adjusts
the abnormality judgment reference value (see Column 5, lines
51-57, 66-68, Column 13, lines 4-20, also discussion below).
As discussed above, Iimura' s overcurrent detection
device, resistor Rs is connected in series path of the power
source (see(+) and(-) connection to Ql, Q4, Rs) which
provides power to the circuit thereby providing closed current
path through the overcurrent detection device Rs is "the current
flowing through the inverter." Iimura detects output at the
voltage divider Rl, R2 junction that is resulting from the
constant/predetermined current through Rs, as R 1, R2 terminals
are connected across Rs or in parallel to Rs.
Ans. 3, 5-6.
Iimura is directed to a circuit overcurrent protection device. See, e.g,
Iimura Abstract. Figure 1 of Iimura is reproduced below.
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Appeal 2014-006311
Application 13/058,691
Figure 1 of Iimura depicts a circuit overcurrent protection device. Iimura 4:
42--44. Figure 1 of Iimura is described in the passages cited by the
Examiner as follows:
if an overcurrent protection level is set to, for example, 10 A
with no external resistor (OQ), the overcurrent protection level
can be adjusted to, for example, 8 A by a series connection of
the external resistor R3. As such, the overcurrent protection
level can be adjusted to a smaller level by selecting a resistor
voltage of the external resistor R3.
if an overcurrent protection level is set to, for example, 10 A
with no external resistor R3, the overcurrent protection level can
be adjusted to, for example, 12 A by a parallel connection of the
external resistor R3.
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Appeal 2014-006311
Application 13/058,691
Iimura 5: 51-57, 63-66. The other passage cited by the Examiner states:
the overcurrent level can be adjusted to a smaller level by
selecting a resistance voltage of the external resistor Rs. The
amplified detection voltage from this amplifier 4 is applied to
the voltage dividing resistors R3 and R4, and one end of the
dividing resistor R4 is connected to the current detection
terminal ISD, and the external resistor Rs is connected between
the same and an external terminal V ss of a ground potential.
The divided voltage can be adjusted by the external resistor Rs.
An overcurrent detection circuit 3 in FIG. 12
embodiment is composed of a comparator, and receives a
reference voltage ref input at one input terminal, and, at the
other input terminal, a divided voltage input of a node between
the voltage dividing resistors R3 and R4. An output of the
comparator is applied to a control electrode of a MOS
semiconductor element to output an overcurrent detection
signal ...
Iimura 13: 3-19. The Examiner's findings with regard to the disputed
limitations are well-supported by Iimura.
We have fully considered Appellants' arguments and find them
unpersuasive. Therefore, we sustain the rejections.
DECISION
The rejections of claims 1-5 and 7-16 are affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § l .136(a)(l )(iv).
AFFIRMED
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