Ex Parte Sahu et al

Patent Trial and Appeal Board

May 29, 2014

11305506 (P.T.A.B. May. 29, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte BRATIN SAHU and ALI-REZA ADL-TABATABAI

Appeal 2012-001146
Application 11/305,506
Technology Center 2100
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Before BRADLEY W. BAUMEISTER, DAVID M. KOHUT, and
ANDREW J. DILLON, Administrative Patent Judges.

DILLON, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-22. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

STATEMENT OF THE CASE
Appellants’ invention is directed to a multi-threaded program wherein
a thread, of a set of threads which share a synchronization barrier, indicates
to the other threads that the thread has reached the synchronization barrier.
Thereafter the thread begins a transactional memory based transaction and
continues execution past the synchronization barrier. See Abstract.
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Claim 1, which is illustrative, is reproduced with key disputed limitations
emphasized:
1. In a multi-threaded program, a method comprising:

a thread, of a set of threads sharing a synchronization barrier,
indicating that the thread has reached the synchronization barrier to
each other thread of the set of threads;

the thread beginning a transactional memory based transaction after
the indicating; and

the thread continuing execution past the synchronization barrier after
beginning the transactional memory based transaction and before all
other threads in the set of threads have reached the synchronization
barrier.

The Examiner relies on the following as evidence of unpatentability:
Tali Moreshet et al, Energy Reduction in Multiprocessor Systems Using
Transactional Memory, August 2005, ISLPED ’05, ACM, pages 331-334
(hereinafter “Moreshet”).

Applicants’ Admitted Prior Art, Application 11/305,506, ¶¶ 2-3 (hereinafter
“AAPA”).

THE REJECTION
The Examiner rejected claims 1-22 under 35 U.S.C. § 103(a) as
unpatentable over Moreshet in view of AAPA. Ans. 4-9.1

1 Throughout this opinion we refer to the Appeal Brief filed May 16, 2011;
the Examiner’s Answer mailed August 3, 2011; and the Reply Brief filed
October 7, 2011.
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CONTENTIONS AND ANALYSIS
We have reviewed the Examiner’s rejection in light of Appellants’
contentions in the Appeal Brief (App. Br. 10-13) and the Reply Brief (Reply
Br. 2-9) that the Examiner has erred. We disagree with Appellants’
conclusions. We adopt as our own (1) the findings and reasons set forth by
the Examiner in the action from which this appeal is taken (Ans. 4-9), and
(2) the reasons set forth by the Examiner in the Examiner’s Answer in
response to Appellants’ Appeal Brief (Ans. 10-11). We highlight and
amplify certain teachings and suggestions of the references as follows.
Only those arguments actually made by the Appellants have been
considered in this decision. Arguments which the Appellants could have
made but chose not to make in the Briefs have not been considered and are
deemed to be waived. See 37 C.F.R. § 41.37 (c)(1)(vii) (2010).
Appellants only provide arguments with respect to independent claim
1 (App. Br. 10-13). Accordingly, we select claim 1 as representative of the
claims, and claims 2-22 will stand or fall with claim 1. See 37 C.F.R.
§ 41.37(c)(1)(vii).
Appellants argue that the cited prior art fails to show or suggest the
provision of an indication that a thread has reached a synchronization barrier
“to each other thread of the set of threads.” App. Br. 12 (emphasis in
original).
The Examiner finds that Moreshet teaches a “thrifty barrier” where
individual threads “spin-wait” while awaiting the arrival of all other threads.
Ans. 10, 11.
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The Examiner finds that as Moreshet teaches that no thread may
execute beyond the barrier, it is inherent that an indication of the arrival of
each thread at the barrier must be available to each thread. Id. at 10.
As further evidence of this finding the Examiner notes that AAPA
discloses a synchronization variable which “is used by threads to
communicate to each other that they have reached a barrier.” Spec. ¶ 2.
In reply, Appellants argue that the cited teachings fail to disclose “the
thread indicating ‘to each other thread’ that the thread has reached the
synchronization.” Reply Br. 7.
We agree with the Examiner. Nothing within Appellants’
Specification discloses that the notification from a thread that it has reached
the synchronization barrier must be made directly “to each other thread of
the set of threads.” Further, Appellants do no expressly argue any portion of
the Specification that would mandate such an interpretation. We find that an
indirect notification, such as posting an indication that is accessible to other
threads that a particular thread has reached the synchronization barrier, can
be broadly, but reasonably interpreted as providing notice “to each other
thread of the set of threads.”
Appellants also argue that the claimed feature of “the thread
beginning a transactional memory based transaction after the indicating” is
not met by the references in view of the alleged failure of the references to
provide the claimed “indicating,” in view of Appellants’ argument set forth
above. App. Br. 11.
For the reasons we enumerated above, we find Appellants’ argument
unpersuasive. We find that nothing within Appellants’ Specification or
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claims that would preclude an indirect notification “to each other thread,” as
proposed by the Examiner’s interpretation of Moreshet and AAPA.
On this basis, and for the reasons we set forth above, we find the
Examiner did not err in rejecting claims 1-22 under 35 U.S.C. § 103(a) as
unpatentable over Moreshet in view of AAPA.

CONCLUSION
The Examiner did not err in rejecting claims 1-22 under § 103.

DECISION
The Examiner’s decision rejecting claims 1-22 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

ELD