Ex Parte Ryu

Board of Patent Appeals and Interferences

Nov 3, 2011

10997199 (B.P.A.I. Nov. 3, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/997,199 11/24/2004 Dong-ryul Ryu 5649-1395 9720
20792 7590 11/04/2011
MYERS BIGEL SIBLEY & SAJOVEC
PO BOX 37428
RALEIGH, NC 27627
EXAMINER
DILLON, SAMUEL A
ART UNIT PAPER NUMBER
2185
MAIL DATE DELIVERY MODE
11/04/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte DONG-RYUL RYU
_____________

Appeal 2009-013733
Application 10/997,199
Technology Center 2100
____________

Before ELENI MANTIS MERCADER, CARL W. WHITEHEAD, JR.,
and BRADLEY W. BAUMEISTER, Administrative Patent Judges.

MANTIS MERCADER, Administrative Patent Judge.

DECISION ON APPEAL

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Appeal 2009-013733
Application 10/997,199

3
Claim 1, reproduced below, is representative of the subject matter on
appeal (emphases added):
1. A method of operating a non-volatile memory device, comprising:
outputting data in response to an alternating sequence of first and
second edges of a read control signal, respectively;
determining whether the read control signal and a write control signal
are in synchronization at one of the first edges; and
stopping an output of the data at the second edge that follows the one
of the first edges of the read control signal responsive to the read control
signal and the write control signal being in synchronization at the one of the
first edges.

THE REJECTIONS
The Examiner relies upon the following as evidence of
unpatentability:
Lysinger US 5,805,523 Sep. 8, 1998
Roohparvar US 6,570,791 B2 May 27, 2003
The following rejections are before us for review:
1. The Examiner rejected claims 1, 3, and 4 under 35 U.S.C. § 102(b)
as being anticipated by Roohparvar.
2. The Examiner rejected claims 2 and 5-23 under 35 U.S.C. § 103(a)
as being unpatentable over Roohparvar in view of Lysinger.

ISSUES
1. Did the Examiner err in determining that Roohparvar teaches the
limitation of “stopping an output of the data at the second edge that follows
the one of the first edges of the read control signal responsive to the read
control signal and the write control signal being in synchronization at the
one of the first edges,” as recited in claim 1?
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Application 10/997,199

4
2. Did the Examiner err in determining the combination of
Roohparvar and Lysinger would have taught or suggested the limitation of
“a data read controller that is configured to generate the sub read control
signal with a frequency double that of the read control signal responsive to
the read control signal, and to generate the disable signal responsive to a
write control signal,” as recited in claim 5?
3. Did the Examiner err in determining the combination of
Roohparvar and Lysinger would have taught or suggested the limitation of
“counting first edges of a flash clock signal that comprises an alternating
sequence of first and second edges responsive to a read recognition signal,”
as recited in claim 12?
4. Did the Examiner err in determining the combination of
Roohparvar and Lysinger would have taught or suggested the limitation of
“a data read controller that is configured to generate the sub flash clock
signal with a frequency double that of the flash clock if a count of first edges
of the flash clock signal is n,” as recited in claim 17?

FINDINGS OF FACT
The following Findings of Fact are supported by a preponderance of
the evidence:
1. Roohparvar teaches that the clock signals CK and CK# determine
the timing of command sampling and data input/output (col. 3, ll. 34-40;
Figs. 3-5; see col. 4, ll. 37-60).
2. Roohparvar teaches that a READ command results in read data
output on the DQ line (col. 4, ll. 41-43; Fig. 3).
Appeal 2009-013733
Application 10/997,199

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3. Roohparvar teaches that a WRITE command initiates a write access
that results in write data input on the DQ line being written to the memory
array (col. 4, ll. 21-28).
4. Lysinger teaches using a two-bit counter of the address to obtain 4-
burst addresses (col. 13, ll. 29-35).

ANALYSIS
Analysis with respect to the rejection of claim 1 under 35 U.S.C. § 102(b) as
anticipated by Roohparvar
Appellant argues (App. Br. 6-7) that Roohparvar does not teach the
limitation of “stopping an output of the data at the second edge that follows
the one of the first edges of the read control signal responsive to the read
control signal and the write control signal being in synchronization at the
one of the first edges” (emphases added), as recited in claim 1. Appellant
contends (App. Br. 7) that in “Roohparvar, the output of data from a read
operation is not stopped responsive to the clock signals CK and CK# being
in synchronization with each other.” Appellant further contends (id.) that, in
contrast to the limitation at issue, Roohparvar’s Figures 3-5 teach outputting
data while the clock signals CK and CK# are in synchronization with each
other. Appellant also argues (id.) that Roohparvar’s clock signal CK and
clock signal CK# are not read and write control signals, respectively.
We are persuaded by Appellant’s arguments. The Examiner interprets
(Ans. 11) Roohparvar’s clock signals CK and CK# as read and write signals,
respectively. We do not agree with the Examiner’s findings because
Roohparvar teaches that the clock signals CK and CK# determine the timing
of command sampling and data input/output (FF 1). Roohparvar teaches
that there are separate Read or Write commands (FF 2-3), and as such, Read
Appeal 2009-013733
Application 10/997,199

6
and Write commands or signals are not the same as the clock signals CK and
CK# (FF 1-3). Therefore, we find that Roohparvar does not teach the
limitation at issue.
For the reasons above, we will not sustain the Examiner’s rejection of
claim 1 or of claims 2-4, which depend from claim 1 and which were not
separately argued.

Analysis with respect to the rejection of claims 5-23 under 35 U.S.C.
§ 103(a) as being unpatentable over Roohparvar in view of Lysinger
Claim 5
Appellant argues (App. Br. 8-9) that the combination of Roohparvar
and Lysinger would not have taught or suggested the limitation of “a data
read controller that is configured to generate the sub read control signal with
a frequency double that of the read control signal responsive to the read
control signal, and to generate the disable signal responsive to a write
control signal,” as recited in claim 5. Appellant argues (App. Br. 8) that
Lysinger does not describe the circuitry of Figure 4A as operating
responsive to a sub read control signal that has a frequency double that of a
read control signal.
We are persuaded by Appellant’s argument. The Examiner finds
(Ans. 13) that Roohparvar’s clock signals CK and CK# correspond to a read
control signal and a write control signal. The Examiner also finds (id.) that
the crossing of the CK and CK# generates a sub read control signal that is
generated with twice the frequency of CK. We do not agree with the
Examiner’s findings for reasons similar to those discussed above for claim 1.
Roohparvar does not teach that clock signals CK and CK# correspond to
Read or Write commands that control the flow of data (FF 1-3). Therefore,
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Application 10/997,199

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the Examiner has not established that the combination of Roohparvar and
Lysinger would have taught or suggested the limitation of “ . . . generate the
sub read control signal with a frequency double that of the read control
signal responsive to the read control signal.”
For the reasons above, we will not sustain the Examiner’s rejection of
claim 5 and of claims 6-11, which depend from claim 5.
Claim 12
Appellant argues (App. Br. 10) that the combination of Roohparvar
and Lysinger does not teach or suggest the limitation of “counting first edges
of a flash clock signal that comprises an alternating sequence of first and
second edges responsive to a read recognition signal,” as recited in claim 12.
Appellant further argues (App. Br. 10; Reply Br. 2) that Lysinger does not
teach that the burst counter counts edges of a clock signal and does not teach
making decisions to output data based on the counts of the edges.
The Examiner finds (Ans. 8, 15) that the combination of Lysinger and
Roohparvar discloses a counter (Lysinger, Fig. 4A) that counts the first
edges of a flash clock (Roohparvar’s clock, Fig. 3) responsive to a read
recognition signal (Roohparvar’s read control signal). We do not agree with
the Examiner’s finding because we do not find support in Lysinger’s Figure
4A to suggest that Lysinger’s burst counter counts “first edges of a flash
clock signal . . . responsive to a read recognition signal.” In contrast,
Lysinger teaches that the counter counts through an entire sequence of the
bits of an address sequence based on the number of bits used to implement
the counter (FF 4).
For the reasons above, we will not sustain the Examiner’s rejection of
claim 12 or of claims 13-16, which depend from claim 12.
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Claim 17
Appellant argues (App. Br. 10) that claim 17 is patentable for at least
the same reasons as claim 12 because claim 17 recites “a data read controller
that is configured to generate the sub flash clock signal with a frequency
double that of the flash clock if a count of first edges of the flash clock
signal is n.”
The Examiner further finds (Ans. 16) that Lysinger counts of the first
edges of Roohparvar’s flash clock signal by relying on Lysinger’s counter
that counts the starting address. We do not agree. For similar reasons as
those articulated above for claim 12, we do not find that the combination of
Roohparvar and Lysinger would have taught or suggested that Lysinger’s
burst counter “count[s] . . . first edges of the flash clock signal” as required
by claim 17 (see FF 4).
For the reasons above, we will not sustain the Examiner’s rejection of
claim 17 or of claims 18-23, which depend from claim 17.

CONCLUSIONS
1. The Examiner erred in determining that Roohparvar teaches the
limitation of “stopping an output of the data at the second edge that follows
the one of the first edges of the read control signal responsive to the read
control signal and the write control signal being in synchronization at the
one of the first edges,” as recited in claim 1.
2. The Examiner erred in determining the combination of Roohparvar
and Lysinger would have taught or suggested the limitation of “a data read
controller that is configured to generate the sub read control signal with a
frequency double that of the read control signal responsive to the read
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Application 10/997,199

9
control signal, and to generate the disable signal responsive to a write
control signal,” as recited in claim 5.
3. The Examiner erred in determining the combination of Roohparvar
and Lysinger would have taught or suggested the limitation of “counting
first edges of a flash clock signal that comprises an alternating sequence of
first and second edges responsive to a read recognition signal,” as recited in
claim 12.
4. The Examiner erred in determining the combination of Roohparvar
and Lysinger would have taught or suggested the limitation of “a data read
controller that is configured to generate the sub flash clock signal with a
frequency double that of the flash clock if a count of first edges of the flash
clock signal is n,” as recited in claim 17.

ORDER
The decision of the Examiner to reject claims 1-23 is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

REVERSED

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