Ex Parte Ryan

Board of Patent Appeals and Interferences

Sep 17, 2009

11432013 (B.P.A.I. Sep. 17, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte KEVIN J. RYAN
____________

Appeal 2009-0031481
Application 11/432,013
Technology Center 2100
____________

Decided: September 18, 2009
____________

Before HOWARD B. BLANKENSHIP, STEPHEN C. SIU, and
JAMES R. HUGHES, Administrative Patent Judges.

BLANKENSHIP, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 70-101, which are all the claims remaining in the
application. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 This appeal is related to Appeal 2009-003815 in Application 10/232,842.
Appeal 2009-003148
Application 11/432,013

2
Invention
Appellant’s invention relates to a memory module having memory
devices coupled by busses to a memory hub. See Abstract.

Representative Claim
70. A memory module comprising;
a substrate;
a memory hub on the substrate operable to receive memory
signals from a memory link port and apply memory signals to the
memory link port, the memory signals comprising at least one of
command, address or data signals, the memory hub being further
operable to translate between memory signals and at least one of
electrical command, address or data signals;
a plurality of memory devices on the substrate, the memory
devices electrically coupled to the memory hub to receive at least one
of command, address, or data signals from the memory hub and to
provide data signals to the memory hub;
a first bus coupling a first one of the memory devices to the
memory hub;
a second bus coupling a second one of the memory devices to
the memory hub;
the first and second buses [sic]2 having substantially a same
length, the length being substantially equal to a shortest distance
between the memory hub and the first one of the memory devices.

2 The plural of “bus” is spelled in different ways in the record, but most
often as “busses.”
Appeal 2009-003148
Application 11/432,013

3
Prior Art
Acton 5,544,319 Aug. 6, 1996
Leddige 6,477,614 B1 Nov. 5, 2002
Hellriegel 6,570,429 B1 May 27, 2003

Examiner’s Rejections
Claims 70-101 stand rejected under 35 U.S.C. § 112, second
paragraph, as being indefinite for failing to particularly point out and
distinctly claim the subject matter which Appellant regards as the invention.
Claims 70-78, 80-94, and 96-101 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Leddige and Hellriegel.3
Claims 79 and 95 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Leddige, Hellriegel, and Acton.

ISSUES
(1) Has the Examiner shown that the claims are indefinite under 35
U.S.C. § 112, second paragraph?
(2) Has Appellant shown that the prior art does not teach two
busses coupling a respective two memory devices to a memory hub, the
busses having substantially a same length, with the length being
substantially equal to a shortest distance between the memory hub and one
of the memory devices?

3 Claim 85 is addressed at page 11 of the Final Rejection and page 10 of the
Answer, but does not appear in the initial listing of the claims rejected over
Leddige and Hellriegel. Claim 101 is treated in similar fashion.
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Application 11/432,013

4
35 U.S.C. § 112, SECOND PARAGRAPH
The legal standard for definiteness is whether a claim reasonably
apprises those of skill in the art of its scope. In re Warmerdam, 33 F.3d
1354, 1361 (Fed. Cir. 1994). The inquiry is merely to determine whether the
claims do, in fact, set out and circumscribe a particular area with a
reasonable degree of precision and particularity. In re Moore, 439 F.2d
1232, 1235 (CCPA 1971). The definiteness of the language employed must
be analyzed -- not in a vacuum, but in light of the teachings of the prior art
and of the particular application disclosure as it would be interpreted by one
possessing the ordinary level of skill in the pertinent art. Id.
Representative claim 70 recites first and second busses having
substantially a same length, the length being substantially equal to a shortest
distance between the memory hub and the first one of the memory devices.
The Examiner’s § 112 rejection of the claims seems based not on one
or the other occurrence of the term “substantially,” nor on the double
occurrence of the term “substantially,” but on the premise that the claims are
indefinite because “a shortest distance” is not clearly defined or easily
ascertainable.
However, since a “bus” having a length of zero would be nonsensical,
the first and second busses each have some physical length that, according to
the claims, is “substantially” equal. That “substantially” equal length, in
turn, is “substantially” equal to “a shortest distance” between the memory
hub and the first one of the memory devices. The “shortest distance”
between the memory hub and the first one of the memory devices must also
be some quantity greater than zero -- i.e., measurable as a “distance” -- that
is the distance between the portion of the memory hub that is nearest to a
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Application 11/432,013

5
corresponding portion of “the first one of the memory devices” that is
nearest to the memory hub. Although the critical recitation may be quite
broad (and not readily seen as supported by the original disclosure),4 the
rejection does not show that the claims are indefinite due to an undefined
“shortest distance.”
We thus agree with Appellant that the rejection does not demonstrate
that the claims are indefinite. We thus do not sustain the rejection of claims
70-101 under 35 U.S.C. § 112, second paragraph.

35 U.S.C. § 103
Claim Groupings
Based on Appellant’s arguments in the Appeal Brief, we will decide
the appeal with respect to the rejections over the prior art on the basis of
claim 70. See 37 C.F.R. § 41.37(c)(1)(vii).

FINDINGS OF FACT
Leddige
Leddige discloses a memory system 113 (Fig. 3) having bus routing
and wiring topology that allows memory devices to have equal latency. A

4 Instant Figure 2 is merely representative of a physical device (i.e., merely a
“block diagram” according to Spec. 5:9-10). Figure 2, for example, does not
show a source of power for memory modules 212-226. If Figure 2 were to
literally describe the invention, the depiction of bus 232, as an example,
might indeed show a bus “substantially equal” to a shortest distance between
memory hub 208 and memory device 214. But if Figure 2 literally describes
the invention, the memory modules might be limited to the requirement of
having all control, data, and address pins or connections on one small
portion of one side of the module.
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first plurality of memory devices 301 are connected in series on the first
memory module 210a on memory bus 321 and a second plurality of memory
devices 302 are connected in series on memory bus 322. Busses 321 and
322 are coupled in parallel with each other and are connected in series with
memory bus 300 via memory repeater hub 320. Col. 3, l. 44 - col. 4, l. 9.
The Examiner finds that memory repeater hub 320 corresponds to the
claimed “memory hub.” Ans. 4.

Hellriegel
Hellriegel discloses a clock distribution tree for use with a
semiconductor chip. Abstract.
As shown in Figure 4, a clock distribution tree 26 comprises a clock
distribution line 42, which divides into branches 44, 46, 48, and 50,
terminating at clock output terminals 52. Col. 3, ll. 45-53.
In another embodiment, not shown, the clock distribution tree is a
starburst pattern having the clock input terminal 30 (Fig. 4) at the center of
the chip, outputting the distribution of the clock in a starburst pattern to the
clock output terminals 52. Col. 4, ll. 14-21.
The clock distribution tree patterns provide that all end points are
equal in distance and in impedance from the source. Id., ll. 22-25.

Specification
“Skew is differential delay between two signals forced to travel
different path lengths. One technique to eliminate skew is to make the path
lengths along which signals are coupled the same length. In this way, signal
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travel time will be the same, thus eliminating any differential delay.” Spec.
1:18-21.5

PRINCIPLES OF LAW
During examination, claims are to be given their broadest reasonable
interpretation consistent with the specification, and the language should be
read in light of the specification as it would be interpreted by one of ordinary
skill in the art. In re Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1364 (Fed.
Cir. 2004) (citations omitted). The Office must apply the broadest
reasonable meaning to the claim language, taking into account any
definitions presented in the specification. Id. (citing In re Bass, 314 F.3d
575, 577 (Fed. Cir. 2002)).
One of ordinary skill in the art must be presumed to know
something about the art apart from what the reference discloses. In re
Jacoby, 309 F.2d 513, 516 (CCPA 1962).
“[W]hen a patent ‘simply arranges old elements with each performing
the same function it had been known to perform’ and yields no more than
one would expect from such an arrangement, the combination is obvious.”
KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 417 (2007) (quoting Sakraida
v. Ag Pro, Inc., 425 U.S. 273, 282 (1976)). The operative question is
“whether the improvement is more than the predictable use of prior art
elements according to their established functions.” Id.

5 Appellant’s counsel adds in the Reply Brief that skew has been eliminated
by increasing shorter path lengths so that they are of equal length with
longer path lengths so that the signals travel the same distance along the
path, without citation to the Specification or any other evidence. See Reply
Br. 2.
Appeal 2009-003148
Application 11/432,013

8

ANALYSIS
Claim Interpretation
Instant claim 70 recites the first and second busses having
substantially a same length, the length being substantially equal to a shortest
distance between the memory hub and the first one of the memory devices.
Appellant argues that the applied prior art does not teach busses
extending to memory devices that can be both “a same length” and
“substantially equal to a shortest distance between the memory hub and the
first one of the memory devices.” App. Br. 16.
Initially, we note that the claims do not recite that the busses have “a
same length,” but recite that the first and second busses have “substantially”
a same length. In any event, the recitation in controversy is described,
according to Appellant, at page 8, lines 9 through 13 of the Specification
(App. Br. 8), reproduced below.

Additionally, because the memory devices 212-226 [Fig. 2] are
placed along the perimeter of the memory hub 208 the
individual busses in the bus system 230-244 can be coupled
directly to the memory hub 208 over the shortest path possible
between each memory device 212-226 and the memory hub
208. This minimizes path lengths between the memory devices
212-226 and the memory hub, which decreases signal travel
times.

Spec. 8:9-14.
The Specification thus teaches that the claim recitation of the first and
second busses having substantially a same length, the length being
substantially equal to a shortest distance between the memory hub and the
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first one of the memory devices, may be met by a bus coupling a “first”
memory device to the memory hub by “substantially” the shortest path
possible, and a second bus coupling a second memory device to the hub
having “substantially” a same length as the bus that couples the hub and the
“first” memory device.
Instant claim 70 recites a memory module “comprising” a “plurality”
of memory devices on a circuit board. Two of any distinct, countable
elements are a “plurality.” The claim also recites “first” and “second”
busses and memory devices, but places no limitation on how the “first” and
“second” respective elements may be chosen, other than that they must be
coupled to the memory hub and the busses are related with respect to a
“substantially equal” length and a “substantially equal” shortest distance.

Leddige
In view of the breadth of instant claim 70, memory bus 321 (Leddige
Fig. 3) and memory bus 322 have “substantially” a same length, the length
being “substantially” equal to a shortest distance between the memory hub
320 and the first one of the memory devices (e.g., the rightmost memory
device on bus 321, or the first memory device of the eight on the bus,
numbering from right to left). Leddige considered alone thus teaches what
Appellant alleges to be missing from the prior art.

Leddige and Hellriegel
We will address Appellant’s further arguments as if Leddige alone
does not teach the argued “substantially” aspects of claim 70.
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Appellant argues there is no apparent reason, teaching, or suggestion
to combine the references because Hellriegel teaches only an arrangement of
wires for a single chip while Leddige teaches only arranging DIMMs (Dual
In-Line Memory Modules) and arranging memory devices in series with
each DIMM.
If a technique has been used to improve one device, and a person of
ordinary skill in the art would recognize that it would improve similar
devices in the same way, using the technique is obvious unless its actual
application is beyond his or her skill. KSR, 550 U.S. at 417. The operative
question is whether the improvement is more than the predictable use of
prior art elements according to their established functions. Id.
Hellriegel teaches at least two ways in which signal lines may be
arranged for simultaneous arrival of signals to disparate destinations. The
teachings include a starburst pattern in which a signal source is arranged at
the center of lines of equal length.
Further, Appellant acknowledges that it was known to eliminate skew
with respect to memory devices by making the path lengths along which
signals are coupled the same length. In addition, Appellant does not allege
that Appellant was the one who discovered that minimizing bus path length
decreases signal travel times and minimizes space required by a bus system
(see Spec. 8:13-16).
Signal lines of substantially equal length were known in the art for the
purpose of reducing skew or latency. One of ordinary skill in the art also
knew that minimizing bus path length decreases signal travel times. There
was nothing unexpected or unpredictable, to one of ordinary skill in the art,
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in arranging memory devices with busses “substantially a same length” from
a memory hub, nor of minimizing bus length.
Appellant further argues that the references “teach against” the
combination because the memory devices of Leddige are arranged “in
series” to achieve the objective of the invention.
The memory devices as shown in Leddige Figure 3 (e.g., on memory
bus 321) may be arranged physically in series, but are not arranged
electrically in series. One skilled in the art would understand that each
memory device on bus 301 is electrically coupled directly to memory
repeater hub because each memory device is directly attached to bus 321,
similar to the electrical coupling shown in Appellant’s “Prior Art” Figure 1
with memory devices on bus 142. The memory devices as shown in
Leddige Figure 3 do not operate by, for example, addressing the rightmost
memory device by propagating a signal through each of the memory devices
to the left of the rightmost memory device, and then retrieving the data as it
is passed through each of the memory devices.
Even assuming that Leddige teaches arranging memory devices
physically in series, Appellant’s argument does not take into account the
breadth of instant claim 70. We also note that Leddige does not describe the
actual dimensions for, as an example, the length of bus 321 as opposed to
the length of bus 322. Appellant seems to rely on dimensions that might be
disclosed by Leddige Figure 3. However, such a position presumes too
much. See In re Wright, 569 F.2d 1124, 1127 (CCPA 1977) (“Absent any
written description in the specification of quantitative values, arguments
based on measurement of a drawing are of little value.”). Figure 3 of
Leddige is a mere representation of an actual device; for example, there is no
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reason for bus 321 to actually extend beyond the rightmost memory device,
because there are no other devices to address beyond the rightmost memory
device.
Further, assuming there is an actual difference between the length of
busses 321 and 322 that are represented by Leddige Figure 3, this record
fails to show that the relative lengths of the busses are not “substantially”
equal, and that the “same length” is not “substantially equal” to, for
example, a shortest distance between memory hub 320 and the rightmost
memory device on bus 321 in Figure 3 of Leddige.
What matters is the object reach of the claim. If the claim extends to
what is obvious, it is invalid under § 103. KSR, 550 U.S. at 419. We are not
persuaded that the Leddige arrangement of memory devices “in series”
teaches against arranging two memory devices with busses having
“substantially a same length” that are coupled to a memory hub, nor against
minimizing bus path length.

CONCLUSIONS OF LAW
(1) The Examiner has not shown that the claims are indefinite
under 35 U.S.C. § 112, second paragraph.
(2) Appellant has not shown that the prior art fails to teach two
busses coupling a respective two memory devices to a memory hub, the
busses having substantially a same length, with the length being
substantially equal to a shortest distance between the memory hub and one
of the memory devices.

Appeal 2009-003148
Application 11/432,013

13
DECISION
The rejection of claims 70-101 under 35 U.S.C. § 112, second
paragraph, is reversed.
The rejection of claims 70-78, 80-94, and 96-101 under 35 U.S.C.
§ 103(a) as being unpatentable over Leddige and Hellriegel is affirmed.
The rejection of claims 79 and 95 under 35 U.S.C. § 103(a) as being
unpatentable over Leddige, Hellriegel, and Acton is affirmed.
Because we have affirmed at least one ground of rejection against
each claim on appeal, the Examiner’s decision is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(f).

AFFIRMED

msc

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