Ex Parte Ryan

Board of Patent Appeals and Interferences

Sep 17, 2009

10232842 (B.P.A.I. Sep. 17, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte KEVIN J. RYAN
____________

Appeal 2009-0038151
Application 10/232,842
Technology Center 2100
____________

Decided: September 18, 2009
____________

Before HOWARD B. BLANKENSHIP, STEPHEN C. SIU, and
JAMES R. HUGHES, Administrative Patent Judges.

BLANKENSHIP, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1-17 and 35-69, which are all the claims remaining in the
application. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 This appeal is related to Appeal 2009-003148 in Application 11/432,013.
Appeal 2009-003815
Application 10/232,842

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Invention
Appellant’s invention relates to a memory module having memory
devices coupled by busses to a memory hub. See Abstract.

Representative Claim
1. A memory module comprising;
a circuit board;
a memory hub on the circuit board operable to receive memory
signals from a high speed memory link and apply memory signals on
the high speed memory link, the memory signals comprising at least
one of command, address or data signals, the memory hub being
further operable to translate between memory signals and electrical
command, address and data signals;
a plurality of memory devices on the circuit board, the memory
devices being located substantially equidistant from the memory hub
and being electrically coupled directly to the memory hub to receive
command, address and data signals from the memory hub and to
provide data signals to the memory hub; and
electrical contacts on the circuit board connected to power
terminals of the memory devices and the memory hub.

Prior Art
Acton 5,544,319 Aug. 6, 1996
Leddige 6,477,614 B1 Nov. 5, 2002
Hellriegel 6,570,429 B1 May 27, 2003

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Examiner’s Rejections
Claims 1-8, 12-17, 35-42, and 46-65 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Leddige and Hellriegel.
Claims 9-11, 43-45, and 66-69 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Leddige, Hellriegel, and Acton.

Claim Groupings
Based on Appellant’s arguments in the Appeal Brief, we will decide
the appeal on the basis of claim 1. See 37 C.F.R. § 41.37(c)(1)(vii).

ISSUE
Has Appellant shown that the Examiner erred in finding that the prior
art teaches a circuit board having two memory devices that are “located
substantially equidistant” from a memory hub?

FINDINGS OF FACT
Leddige
Leddige discloses a memory system 113 (Fig. 3) having bus routing
and wiring topology that allows memory devices to have equal latency. A
first plurality of memory devices 301 are connected in series on the first
memory module 210a on memory bus 321 and a second plurality of memory
devices 302 are connected in series on memory bus 322. Busses 321 and
322 are coupled in parallel with each other and are connected in series with
memory bus 300 via memory repeater hub 320. Col. 3, l. 44 - col. 4, l. 9.
The Examiner finds that memory repeater hub 320 corresponds to the
claimed “memory hub.” Ans. 3.
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Hellriegel
Hellriegel discloses a clock distribution tree for use with a
semiconductor chip. Abstract.
As shown in Figure 4, a clock distribution tree 26 comprises a clock
distribution line 42, which divides into branches 44, 46, 48, and 50,
terminating at clock output terminals 52. Col. 3, ll. 45-53.
In another embodiment, not shown, the clock distribution tree is a
starburst pattern having the clock input terminal 30 (Fig. 4) at the center of
the chip, outputting the distribution of the clock in a starburst pattern to the
clock output terminals 52. Col. 4, ll. 14-21.
The clock distribution tree patterns provide that all end points are
equal in distance and in impedance from the source. Id., ll. 22-25.

Specification
“Skew is differential delay between two signals forced to travel
different path lengths. One technique to eliminate skew is to make the path
lengths along which signals are coupled the same length. In this way, signal
travel time will be the same, thus eliminating any differential delay.” Spec.
1:18-21.2

2 Appellant’s counsel adds in the Reply Brief that skew has been eliminated
by increasing shorter path lengths so that they are of equal length with
longer path lengths so that the signals travel the same distance along the
path, without citation to the Specification or any other evidence.
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PRINCIPLES OF LAW
During examination, claims are to be given their broadest reasonable
interpretation consistent with the specification, and the language should be
read in light of the specification as it would be interpreted by one of ordinary
skill in the art. In re Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1364 (Fed.
Cir. 2004) (citations omitted). The Office must apply the broadest
reasonable meaning to the claim language, taking into account any
definitions presented in the specification. Id. (citing In re Bass, 314 F.3d
575, 577 (Fed. Cir. 2002)).
One of ordinary skill in the art must be presumed to know
something about the art apart from what the reference discloses. In re
Jacoby, 309 F.2d 513, 516 (CCPA 1962).
“[W]hen a patent ‘simply arranges old elements with each performing
the same function it had been known to perform’ and yields no more than
one would expect from such an arrangement, the combination is obvious.”
KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 417 (2007) (quoting Sakraida
v. Ag Pro, Inc., 425 U.S. 273, 282 (1976)). The operative question is
“whether the improvement is more than the predictable use of prior art
elements according to their established functions.” Id.

ANALYSIS
Claim Interpretation
Instant claim 1 recites a plurality of memory devices on the circuit
board, the memory devices being located substantially equidistant from the
memory hub and being electrically coupled directly to the memory hub to
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receive command, address and data signals from the memory hub and to
provide data signals to the memory hub.
Appellant argues that the applied prior art does not teach memory
devices being located “substantially equidistant” from the memory hub.
Appellant tells us the limitation is described at page 4, lines 26 through 28,
and page 7, line 28 through page 8, line 11 of the Specification. App. Br. 8.
The Specification at page 4 refers to Figure 2, described as “one
embodiment” of the invention. The most relevant portion of the
Specification section at pages 7 and 8 is reproduced below.
In a preferred embodiment, the memory hub 208 [Fig. 2] is
placed at the center of the module 201. Placing the memory
hub 208 at the center of the module 201 makes it easier for each
individual bus in the bus system 230-244 coupling each
memory device 212-226 to the memory hub 208 to be
substantially the same length. As a result, travel times for
electrical command, address and data signals between each
memory device 212-226 and the memory hub 208 are the same
regardless of which memory device 212-226 is in
communication with the hub 208. Consequently, signals
traveling to and from the hub 208 to different memory devices
212-226 do not experience differential delay, and thus skew is
eliminated.

Spec. 8:1-9.
The Specification thus teaches that the Figure 2 embodiment --
placing the memory hub 208 as the center of the module 201 -- helps avoid
differential delay between signals with respect to the hub and memory
devices. However, neither instant claim 1 nor the remainder of the
Specification requires that the invention is limited to the particular topology
of Figure 2. Nor does the Specification set forth any particular limiting
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factors for what might be considered “substantially equidistant” as recited in
claim 1.
Instant claim 1 recites that the memory devices are located
substantially equidistant from the memory hub. The claim is silent with
respect to what the relative lengths of the signal lines may be.
Instant claim 1 also recites a memory module “comprising” a
“plurality” of memory devices on a circuit board. Two of any distinct,
countable elements are a “plurality.”

Leddige
In view of the breadth of instant claim 1, at least the rightmost
(eighth) memory device on memory bus 321 (Leddige Fig. 3) and the
rightmost (eighth) memory device on memory bus 322 are “substantially
equidistant” from memory hub 320. Leddige considered alone thus teaches
what Appellant alleges to be missing from the prior art.

Leddige and Hellriegel
We will address Appellant’s further arguments as if Leddige alone
does not teach the “substantially equidistant” aspect of claim 1.
Appellant argues there is no apparent reason, teaching, or suggestion
to combine the references because neither Leddige nor Hellriegel teaches
that arranging memory devices at equal distances relative to a memory hub
is a viable means for reducing skew or latency.
If a technique has been used to improve one device, and a person of
ordinary skill in the art would recognize that it would improve similar
devices in the same way, using the technique is obvious unless its actual
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application is beyond his or her skill. KSR, 550 U.S. at 417. The operative
question is whether the improvement is more than the predictable use of
prior art elements according to their established functions. Id.
Hellriegel teaches at least two ways in which signal lines may be
arranged for simultaneous arrival of signals to disparate destinations. The
teachings include a starburst pattern in which a signal source is arranged at
the center of lines of equal length.
Further, Appellant acknowledges that it was known to eliminate skew
with respect to memory devices by making the path lengths along which
signals are coupled the same length.
Even if we assume that neither Leddige nor Hellriegel teaches that
arranging memory devices at equal distances relative to a memory hub is a
viable means for reducing skew or latency, making signal lines of equal
length was known in the art for the purpose of reducing skew or latency.
There was nothing unexpected or unpredictable, to one of ordinary skill in
the art, in arranging memory devices “substantially equidistant” from a
memory hub.
Appellant further argues that the references “teach against” the
combination because the memory devices of Leddige are arranged “in
series” to achieve the objective of the invention.
The memory devices as shown in Leddige Figure 3 (e.g., on memory
bus 321) may be arranged physically in series, but are not arranged
electrically in series. One skilled in the art would understand that each
memory device on bus 301 is electrically coupled directly to memory
repeater hub because each memory device is directly attached to bus 321,
similar to the electrical coupling shown in Appellant’s “Prior Art” Figure 1
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with memory devices on bus 142. The memory devices as shown in
Leddige Figure 3 do not operate by, for example, addressing the rightmost
memory device by propagating a signal through each of the memory devices
to the left of the rightmost memory device, and then retrieving the data as it
is passed through each of the memory devices.
Even assuming that Leddige teaches arranging memory devices
physically in series, Appellant’s argument does not take into account the
breadth of instant claim 1. If we further assume that claim 1 somehow
requires that the “electrical coupling” between a plurality (e.g., two) memory
devices and the memory hub be “substantially” equal in path length, we note
that Leddige discloses that the memory devices are arranged for equal
latency. We also note that Leddige does not describe the actual dimensions
for, as an example, the length of bus 321 to the rightmost memory device on
the bus or the length of bus 322 to the rightmost memory device on that bus.
Appellant seems to rely on dimensions that might be disclosed by Leddige
Figure 3. However, such a position presumes too much. See In re Wright,
569 F.2d 1124, 1127 (CCPA 1977) (“Absent any written description in the
specification of quantitative values, arguments based on measurement of a
drawing are of little value.”).
Further, assuming there is an actual difference between the length of
busses 321 and 322 that are represented in Leddige Figure 3, this record fails
to show that the memory devices at the ends of the busses are not
“substantially equidistant” from the memory hub. Even if the bus path
lengths are not “substantially” equal, Figure 3 of Leddige at least suggests
that the rightmost memory devices on respective busses 321 and 322 are
“substantially equidistant” from memory hub 320, as demonstrated by the
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relative lengths of straight lines that can be drawn from a surface of the
memory hub to a surface of each device.
What matters is the object reach of the claim. If the claim extends to
what is obvious, it is invalid under § 103. KSR, 550 U.S. at 419. We are not
persuaded that the Leddige arrangement of memory devices “in series”
teaches against arranging memory devices “substantially equidistant” from a
memory hub.

CONCLUSION OF LAW
Appellant has not shown that the Examiner erred in finding that the
prior art teaches a circuit board having two memory devices that are “located
substantially equidistant” from a memory hub.

DECISION
The rejection of claims 1-8, 12-17, 35-42, and 46-65 under 35 U.S.C.
§ 103(a) as being unpatentable over Leddige and Hellriegel is affirmed.
The rejection of claims 9-11, 43-45, and 66-69 under 35 U.S.C.
§ 103(a) as being unpatentable over Leddige, Hellriegel, and Acton is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(f).

AFFIRMED

Appeal 2009-003815
Application 10/232,842

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