Ex Parte Rupley

Patent Trial and Appeal Board

Sep 20, 2016

12900124 (P.T.A.B. Sep. 20, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/900,124 10/07/2010 Jeff Rupley
109712 7590 09/22/2016
Advanced Micro Devices, Inc,
c/o Davidson Sheehan LLP
8834 North Capital of TX Hwy
Suite 100
Austin, TX 78759
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
1458-100265 7161
EXAMINER
LI,ZHUOH
ART UNIT PAPER NUMBER
2133
NOTIFICATION DATE DELIVERY MODE
09/22/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docketing@ds-patent.com
beatrice. zepeda@ds-patent.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JEFF RUPLEY
Appeal2014-007758
Application 12/900, 124
Technology Center 2100
Before ALLEN R. MacDONALD, CARLA M. KRIVAK, and
HUNG H. BUI, Administrative Patent Judges.
KRIVAK, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from a final rejection of
claims 1-22. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.
Appeal2014-007758
Application 12/900, 124
STATEMENT OF THE CASE
Appellant's invention is directed to "register caching in processor-
based systems" (Spec. i-f l ).
Independent claim 1, reproduced below, is exemplary of the subject
matter on appeal.
1. A method, comprising:
mapping a first set of architected registers defined by a first
instruction set to a memory outside of a plurality of
physical registers, wherein the plurality of physical
registers are configured to map to the first set of
architected registers, a second set of architected registers
defined by a second instruction set, and a set of rename
registers; and
adding the physical registers corresponding to the first set of
architected registers to the set of rename registers in
response to said mapping.
REFERENCES and REJECTIONS
The Examiner rejected claims 1-22 under 35 U.S.C. § 103(a) based
upon the teachings of Gschwind (US 2007/0162726 Al; published July 12,
2007), Noyes (US 8,140,780 B2; issued Mar. 20, 2012), and Jourdan (US
2004/0015904 Al; published Jan. 22, 2004).
ANALYSIS
Appellant contends the Examiner erred in finding Noyes discloses
"mapping a first set of architected registers defined by a first instruction set
to a memory outside of a plurality of physical registers," as recited in claim
1 (App. Br. 5). Appellants also assert claim 1 maps registers to memory;
whereas Noyes maps memory to registers (App. Br. 5---6).
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Appeal2014-007758
Application 12/900, 124
We do not agree with Appellants. Rather, we agree with and adopt
the Examiner's findings as our own (Ans. 2---6). Particularly, we agree with
the Examiner that Noyes "teaches MMU (96, figure 13) may use address
map (99, figure 13) to map physical memory locations of the system (94,
figure 13) and other device (93, figure 3)" and map to "locations outside the
memory, such as registers (97, figure 13, col. 11 line 52 through col. 12 line
7[)]" (Ans. 2-3). We also agree with the Examiner that Noyes' registers 97
can be seen as memories (memories include registers) outside of the
plurality of physical registers (Ans. 3). Although Appellants contend the
Examiner erred because Noyes maps to physical addresses (Fig. 13, address
map 99) between registers 97 and memory 95, "the address map does not
provide any mapping of any register to memory 95" (App. Br. 6), we
disagree. The Examiner finds Gschwind discloses the mapping step except
for specifically teaching mapping a set of registers to memory outside of a
plurality of physical registers as claimed, relying on Noyes for this teaching:
The address map 99, however, may have a finite
number of addresses that can be mapped to physical
memory locations of the system 94 and other
devices, such as device 93.
Noyes col. 11, 11. 52-56 (emphasis added).
Noyes' device 93 is a memory outside the physical registers (memory
locations) of the system 94 and includes registers 97 (Fig. 13). We agree
with the Examiner that Noyes discloses a set of registers mapped to memory
outside the physical registers (Ans. 3), and the combination of Noyes and
Gschwind teaches the mapping step of claim 1 (Final Act. 2-3). The
Examiner has also made reasonable findings regarding Jourdan's disclosure
teaching adding physical registers corresponding to architected registers to a
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Appeal2014-007758
Application 12/900, 124
set of rename registers (Ans. 3--4; Jourdan Fig. 2, renaming unit 208; iii! 17-
21).
Thus, we sustain the Examiner's rejection of independent claim
1 and independent claims 9 and 1 7, and for which no new arguments
were provided (App. Br. 7-9).
The Examiner finds Gschwind discloses re-mapping registers
in response to demand usage associated with instructions as recited in
dependent claims 3, 6-8, 11, 12, and 14--16 (Final Act. 4--5; Ans. 5).
We do not agree. Paragraph 14 of Gschwind discloses a register map
table 520 updated with register names specified by a free-register
queue (Ans. 5; Gschwind ifl4). However, we do not see how this
register map table 520 teaches re-mapping registers in response to
demand usage associated with instructions as claimed. Thus, we do
not sustain the Examiner's rejection of claims 3, 6-8, 11, 12, and 14--
16, or claim 4, which depends from claim 3.
With respect to claims 2, 5, 10, 13, 18, 19, 21, and 22, we
sustain the Examiner's rejection as Appellants assert these claims are
allowable by virtue of depending from independent claims 1, 9, 17,
and 20. As we found claims 1, 9, 17, and 20 obvious over the cited
references, claims 2, 5, 10, 13, 18, 19, 21, and 22 fall therewith.
DECISION
The Examiner's decision rejecting claims 1, 2, 5, 9, 10, 13, and 17-22
is affirmed.
The Examiner's decision rejecting claims 3, 4, 6-8, 11, 12, and 14--16
is reversed.
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Appeal2014-007758
Application 12/900, 124
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED-IN-PART
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