Ex Parte Rulke et al

Patent Trial and Appeal Board

Mar 27, 2013

10987484 (P.T.A.B. Mar. 27, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/987,484 11/12/2004 Hartmut Rulke 2162.113000/DE0462 1848
10742 7590 03/27/2013
GLOBALFOUNDRIES INC.
c/o Williams, Morgan & Amerson
10333 Richmond , Suite 1100
Houston, TX 77042
EXAMINER
MALDONADO, JULIO J
ART UNIT PAPER NUMBER
2898
MAIL DATE DELIVERY MODE
03/27/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte HARTMUT RULKE, KATJA HUY and MARKUS LENSKI
____________

Appeal 2010-011200
Application 10/987,484
Technology Center 2800
____________

Before CARL W. WHITEHEAD, JR., ERIC S. FRAHM and ANDREW J.
DILLON, Administrative Patent Judges.

WHITEHEAD, JR., Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2010-011200
Application 10/987,484

2
STATEMENT OF THE CASE
Appellants are appealing claims 1, 2 and 4-16. Appeal Brief 2. We
have jurisdiction under 35 U.S.C. § 6(b) (2012).
We reverse.

Introduction
The invention is directed to a method of forming spacer elements in a
semiconductor device. Appeal Brief 3.

Illustrative Claim
1. A method of forming spacer elements, the method comprising:
forming a gate electrode above a semiconductor region;
forming at least one trench isolation in the semiconductor region,
thereby creating a compressive stress in a channel region beneath the gate
electrode;
depositing in a high frequency plasma atmosphere a spacer layer
having tensile stress over said gate electrode and said semiconductor region,
wherein depositing said spacer layer comprises controlling a bias voltage in
said high frequency plasma atmosphere to adjust a degree of tensile stress in
said spacer layer such that the tensile stress in said spacer layer compensates
for the compressive stress in the channel region; and
etching said spacer layer to form a spacer element having tensile
stress.

Appeal 2010-011200
Application 10/987,484

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Rejections on Appeal
Claims 1, 2 and 4-14 stand rejected under 35 U.S.C. §103(a) as being
unpatentable over Chidambarrao (U.S. Patent Application Publication
Number 2005/0040460 A1; published February 24, 2005), Tang (U.S. Patent
Application Publication Number 2003/0199175 A1; published October 23,
2003) and Ngo (U.S. Patent 6,333,218 B1; issued December 25, 2001).
Answer 3-9.

Claims 15 and 16 stand rejected under 35 U.S.C. §103(a) as being
unpatentable over Chidambarrao, Tang, Ngo and Ito, “Mechanical Stress
Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor
Design” International Electron Devices Meeting: Technical Digest (IEDM),
247-250 (2000). Answer 10-11.

Issue on Appeal
Do Chidambarrao, Tang, Ngo, either alone or in combination, disclose
“wherein depositing said spacer layer comprises controlling a bias voltage in
said high frequency plasma atmosphere to adjust a degree of tensile stress in
said spacer layer such that the tensile stress in said spacer layer compensates
for the compressive stress in the channel region” as recited in claim 1?

ANALYSIS
Appellants contend that the claimed invention has a spacer layer that
has a tensile stress that is adjusted by controlling a bias voltage in the high
frequency plasma atmosphere. Appeal Brief 6. “The degree of tensile stress
Appeal 2010-011200
Application 10/987,484

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in the spacer layer is adjusted so that the tensile stress in the spacer layer
compensates for the compressive stress in the channel region.” Id.
The Examiner finds that:
Chidambarrao discloses controlling frequency power,
among other parameters, to adjust a degree of stress, either
tensile or compressive (Chidambarrao, [0027]). However,
Chidambarrao fails to expressly disclose controlling a bias
voltage to adjust a degree of tensile stress. Nevertheless,
Tang discloses a method of forming spacer structures
comprises the steps of forming a gate electrode over a
semiconductor substrate; and forming a spacer layer in a
high frequency plasma atmosphere, wherein depositing
said spacer layer comprises controlling said high
frequency plasma atmosphere, and said high frequency
changes result in changes in a bias voltage (Tang, [0004],
[0009] - [0012], [0022] - [0031] and [0037] -[0041]).
Since, the combination of Chidambarrao and Tang
discloses that changes in the frequency affects the voltage,
and said frequency controls the degree of tensile stress on
the deposited layer, it is inherent that changes in the bias
voltage of the combination of Chidambarrao and Tang
affects the degree of tensile stress of the deposited layer.
And as stated in the rejection hereinabove, it would have
been obvious to one of ordinary skill in the art at the time
the invention was made to combine the teachings of
Chidambarrao and Tang to enable forming the spacer layer
of Chidambarrao according to the teachings of Tang for
the further advantage of forming spacer layers with high
conformity (Tang, [0011] and [0025]).

Answer 12-13.
Appellants argue that:

Chidambarrao and Tang are both completely silent with
regard to any connection or relationship between a bias
voltage and a tensile stress in a layer. The Examiner has
Appeal 2010-011200
Application 10/987,484

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not provided any evidence that the relationship between
the bias voltage and the tensile stress was known to a
person of ordinary skill in the art regardless of whether or
not this relationship was inherent. Applicants therefore
respectfully submit that the Examiner has improperly used
hindsight reasoning (informed by the teachings of the
present application) to allege that an inherent relationship
existed between the bias voltage and the tensile stress.

Appeal Brief 7.
We do not agree with the Examiner’s findings and we find
Appellants’ arguments to be persuasive.
The Examiner finds that Tang discloses high frequency changes that
result in changes in the bias voltage (Tang, [0004], [0009]-[0012], [0022]-
[0031] and [0037]-[0041]); however, we cannot substantiate the Examiner’s
findings because, although the Examiner indicated several paragraphs that
he relied upon, Tang is silent in regard to the bias voltage. See Answer 12.
There are several factors that could affect the change in the high and low
frequency RF power disclosed in Tang; however, there is no indication that
the change was achieved by manipulating a bias voltage. Therefore, we find
Appellants’ arguments that the Examiner has not provided evidence that
there is a connection between a bias voltage and tensile stress within a layer
disclosed within either Chidambarrao and/or Tang are persuasive. See
Appeal Brief 7. Ngo does not address the deficiency of the Chidambarrao
and Tang combination.
We reverse the Examiner’s obviousness rejection of independent
claim 1 as well as dependent claims 2 and 4-16.

Appeal 2010-011200
Application 10/987,484

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DECISION
The obviousness rejection of claims 1, 2 and 4-16 is reversed.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See 37
C.F.R. § 41.50(f).

REVERSED

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