Ex parte ROTSTAIN

Board of Patent Appeals and Interferences

May 28, 1998

07970260 (B.P.A.I. May. 28, 1998)

Application for patent filed November 2, 1992.1
1
THIS OPINION WAS NOT WRITTEN FOR PUBLICATION
The opinion in support of the decision being entered today
(1) was not written for publication in a law journal and
(2) is not binding precedent of the Board.
Paper No. 22
UNITED STATES PATENT AND TRADEMARK OFFICE
__________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
__________
Ex parte JEHOSHUA S. ROTSTAIN
__________
Appeal No. 96-3767
Application 07/970,2601
__________
ON BRIEF
__________
Before THOMAS, FLEMING, and TORCZON, Administrative Patent
Judges.
THOMAS, Administrative Patent Judge.
DECISION ON APPEAL
Appellant has appealed to the Board from the examiner’s
final rejection of claims 1, 4, 5, and 10 to 32, which constitute
all the claims remaining in the application.
Appeal No. 96-3767
Application 07/970,260
2
Representative claim 1 is reproduced below:
1. A method of performing division operations, including
the following steps:
inputting a dividend and a divisor;
determining whether a first value is present in a cache
memory, the first value representing the value of the divisor;
reading a second value from the cache memory as a reciprocal
of the divisor, the second value corresponding to the first value
and representing the reciprocal of the first value, and finding
the quotient by multiplying the second value and the dividend, in
the event that the first value is determined to be present in the
cache memory; and
finding the quotient of the dividend and the divisor by
determining a reciprocal of the divisor and multiplying the
reciprocal and the dividend, in the event that the first value is
determined to not be present in the cache memory.
The following references are relied on by the examiner:
Sierra 3,648,038 Mar. 7, 1972
Richardson 5,260,898 Nov. 9, 1993
(filing date Mar. 13, 1992)
All claims on appeal stand rejected under 35 U.S.C. § 103.
As evidence of obviousness, the examiner relies upon Richardson
alone as to claims 10 to 12 and 20 to 22. As to claims 1, 4, 5,
Appeal No. 96-3767
Application 07/970,260
Page 2 of the Examiner’s Answer indicates that the2
examiner has withdrawn a rejection of certain claims under
35 U.S.C. § 101 set forth in the Final Rejection.
3
13 to 19 and 23 to 32, the examiner relies upon the collective
teachings of Richardson and Sierra.2
Rather than repeat the positions of the appellant and the
examiner, reference is made to the Briefs and the Answer for the
respective details thereof.
OPINION
Both rejections under 35 U.S.C. § 103 are reversed.
Turning initially to the rejection of claims 10 to 12 and 20
to 22 under 35 U.S.C. § 103 in light of Richardson alone,
independent claim 10 sets forth various conditions. Upon a
determination of whether a first value is present in a cache
memory, a further determination is made whether a second value is
present in the same memory. Again, upon a determination that
this second value is present in the cache memory a read operation
is performed with the final result of finding the remainder of a
quotient. Corresponding operations are performed in apparatus
independent claim 20.
Appeal No. 96-3767
Application 07/970,260
4
As a result of our study of Richardson and consideration
with appellant’s arguments, the examiner’s position and the
subject matter of these claims in this rejection, we essentially
agree with the appellant’s statements set forth here:
Claim 10 recites separate steps for determining the
presence of each of the input dividend and divisor in
the cache memory, and the step of determining whether
the dividend is present in the cache memory is
conditional upon the divisor being present in the cache
memory. If both the divisor and the dividend are
present in the cache memory, the quotient of the
dividend and the divisor is read out from the cache
memory and is used to find the remainder. Thus, a
single cache access occurs, but the presence of the
dividend and divisor is determined separately. (Brief,
page 13)
Richardson fails to disclose the performance of a
remainder operation. Furthermore, result cache look-
ups in Richardson are performed using a single
representation of the input operand pair, and
Richardson does not teach or suggest that each operand
of an operand pair may be searched for separately, as
required by the present claims. (Brief, page 14)
Since we have reversed the rejection of independent claims 10 and
20, we also reverse the rejection of their respective dependent
claims 11, 12, 21, and 22.
Turning lastly to the rejection of the remaining claims
under 35 U.S.C. § 103 in light of the collective teachings of
Richardson in view of Sierra, we reverse the rejection of
independent claims 14, 16, 24, and 26 essentially for the reasons
Appeal No. 96-3767
Application 07/970,260
5
set forth with our reversal as to independent claims 10 and 20.
Claims 14, 16, 24, and 26 set forth remainder operations based
upon the conditional determinations of the type set forth in
independent claims 10 and 20 on appeal. Even if we were to agree
with the examiner of the proper combinability of Ricihardson and
Sierra, Sierra fails to cure these noted deficiencies with
respect to Richardson’s teachings.
We turn lastly to independent claims 1, 4, 5, 30, and 31,
which all recite in some form method or apparatus versions of
division operations by multiplying reciprocals of divisors to
yield a quotient. Inasmuch as Richardson fails to disclose the
specifics of the divider circuits 140, such as in Figure 2, but
only generally discloses this element, we agree with the
examiner’s position that it would have been obvious for the
artisan to have utilized the specific arithmetic circuit shown in
Sierra for performing the representative division operations only
generally disclosed in Richardson.
However, we do not agree with the examiner’s view expressed
at page 5 of the Answer that it would have been obvious for the
artisan to have provided “the cache memory [of Richardson] with a
reciprocal function in order to quickly obtain the reciprocal of
the divisor without redundantly recomputing the reciprocal in the
Appeal No. 96-3767
Application 07/970,260
6
event that the divisor is determined to be present in the cache
memory but not the dividend.” In accordance with the last
paragraph of column 2 of Richardson and the beginning paragraph
of column 3, there are essentially parallel operations taking
place in Richardson’s circuits such as in representative Figure 1
where the result cache 10 is accessed contemporaneously with the
functioning of the arithmetic circuit 40. If a “hit” occurs in
the result cache 10, the halt signal 60 is issued to stop the
operation in the arithmetic circuit 40.
Thus, even if it would have been obvious to combine the
structure of Sierra to embody an arithmetic circuit in
Richardson, it appears that the feature of determining whether a
first value is present in a cache memory before other operations
are taking place as set forth in independent claim 1 on appeal
would not have been performed. It appears that the combination
would have yielded their contemporaneous access to the cache
memory at the same time that the reciprocal is being determined
according to Sierra’s teachings embodying the arithmetic circuit
as substituted in Richardson from Sierra. Claim 1 is conditional
in that if the first value is found in the cache the truncated
cache operation occurs, but at the same time, the claim requires
that if the first value is not present in the cache memory, a
Appeal No. 96-3767
Application 07/970,260
7
conventional reciprocal determination is then made. The
combination of teachings does not yield this function in a
relationship of the conditions set forth in this representative
claim. As such, we are in general agreement with appellant’s
observations reflected at the bottom of page 19 and the top of
page 20 of the principal Brief on appeal that the combination
would have necessitated a modification beyond the mere
substitution of the divider of Sierra for the divider in
Richardson.
We reach a similar result even when considering the Figure 5
embodiment of Richardson which details the use of a cache memory
with a single operand arithmetic unit. This is so because the
claims require the inputting of a dividend and a divisor rather
than just a single input. We also reverse the rejection of
claims 4, 5, 30, and 31 since the examiner has not detailed any
reason of obviousness from the combination of references for all
of the features in each of these claims.
Appeal No. 96-3767
Application 07/970,260
8
In view of the foregoing, we have reversed the outstanding
rejections under 35 U.S.C. § 103 of claims 1, 4, 5, and 10 to 32.
REVERSED
James D. Thomas )
Administrative Patent Judge )
)
)
) BOARD OF PATENT
Michael R. Fleming ) APPEALS AND
Administrative Patent Judge ) INTERFERENCES
)
)
)
Richard Torczon )
Administrative Patent Judge )
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