Ex Parte Roohparvar

Board of Patent Appeals and Interferences

Jul 6, 2012

11127619 (B.P.A.I. Jul. 6, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte FRANKIE F. ROOHPARVAR
____________________

Appeal 2010-003300
Application 11/127,619
Technology Center 2800
____________________

Before JOSEPH L. DIXON, ST. JOHN COURTENAY III, and
ANDREW J. DILLON, Administrative Patent Judges.

COURTENAY, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-003300
Application 11/127,619

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STATEMENT OF CASE
Appellant appeals under 35 U.S.C. § 134 from a final rejection of
claims 9, 12, 23-25, 28, 30, 31, and 34-37. We have jurisdiction under 35
U.S.C. § 6(b).
We affirm.
Invention
The claims are directed to a method for erasing a memory device.
Claim 9, reproduced below, is illustrative of the claimed subject matter:
9. A method for erasing a memory device having a memory
array comprising a normal memory sub-block and a shadow
memory sub-block that is of substantially the same size as the
normal memory sub-block, the sub-blocks together making up a
memory block, the method comprising:

determining which of the normal memory sub-block or
the shadow memory sub-block is a selected sub-block to be
erased, wherein the normal memory sub-block is not separated
from the shadow memory sub-block by a select transistor;

preventing further erase operations only on the shadow
memory sub-block if a quantity of program/erase cycles
performed on the shadow memory sub-block is greater than a
predetermined threshold, wherein preventing further erase
operations comprises biasing each word line of the shadow
memory sub-block at a same voltage that inhibits the erase
operations;

biasing word lines of the selected sub-block with an erase
voltage;
floating word lines of the unselected sub-block; and
biasing a substrate in which the memory block is formed
with a voltage greater than VCC.

(disputed limitations emphasized).
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REJECTIONS
Claims 9, 12, 23-25, 28, 30, 31 and 34-37 stand rejected under 35
U.S.C § 112, first paragraph, as failing to comply with the written
description requirement.1
Claim 9 stands rejected under 35 U.S.C § 103(a) as being
unpatentable over the combination of Hosono (U.S. Patent Application
Publication No. 2005/0018489 A1, published Jan. 27, 2005) and Chen (U.S.
Patent No. 6,944,063 B2 (filed Jan. 28, 2003)).
Claim 12 stands rejected under 35 U.S.C § 103(a) as being
unpatentable over the combination of Hosono, Chen, and Lee (U.S. Patent
Application Publication No. 2005/0204187 A1, published Sept. 15, 2005).
Claims 23 and 24 stand rejected under 35 U.S.C § 103(a) as being
unpatentable over the combination of Hosono, Chen, Appellant’s Admittted
Prior Art (hereinafter “APA”), and Miyamoto (U.S. Patent No. 5,452,249
(filed Mar. 21, 1994).
Claims 25, 28, 30, 31, and 35-37 stand rejected under 35 U.S.C
§ 103(a) as being unpatentable over the combination of Hosono, APA, and
Miyamoto.
Claim 34 stands rejected under 35 U.S.C § 103(a) as being
unpatentable over the combination of Hosono, APA, Miyamoto, and Chen.

ANALYSIS
35 U.S.C § 112, first paragraph, written description
Issue: Under § 112, does the originally-filed Specification reasonably
convey to the artisan that Appellant had possession of the claimed limitation:

1 See Final Office Action, mailed Dec. 24, 2008, p. 2.
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preventing further erase operations only on the shadow memory
sub-block if a quantity of program/erase cycles performed on
the shadow memory sub-block is greater than a predetermined
threshold, wherein preventing further erase operations
comprises biasing each word line of the shadow memory sub-
block at a same voltage that inhibits the erase operations,]
within the meaning of independent claims 9 and 23 (emphasis added)?
Appellant presents the following contentions:
Appellant agrees that the present specification does not
specifically state that “prohibiting” a program/erase operation
is performed by providing “inhibiting” voltages to the word
lines. However, paragraph 0026 states that the method “...
biases the selected word lines of the memory block to be erased
(e.g., normal memory block or shadow memory block) at 0V.
The unselected word lines of the remaining memory block are
biased at some high voltage (e.g., 20V) that would inhibit erase
of those rows.” This paragraph makes it clear that selected
word lines are erased and unselected word lines are not erased.
Paragraph 0029 clearly states that an inhibit voltage is used on
the unselected word lines. These passages, as well as others,
make it clear to any reader of the present specification that an
inhibit voltage will stop an erase operation of any row that is so
biased. Thus, one skilled in the art upon reading the present
specification could certainly come to the conclusion that
“prohibiting” a program/erase operation can be accomplished
by providing “inhibit voltages”. Prohibiting erase of memory
cells has the same physical result as inhibiting erase of memory
cells, i.e., the memory cells are not erased.

. . . .

Paragraph 0030 of the present specification clearly states
that “ ... instead of biasing the unselected word lines at some
high inhibit voltage, the unselected word lines can be left
floating. Since the tub is biased at some high voltage, such as
20V, the floating word lines would be coupled up substantially
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close to that high tub voltage. This would perform the same
inhibit function as in the bias voltage greater than VCC].” This
clearly provides the necessary written description for
Appellant’s claim 25 element that states “all word lines of the
shadow memory block are coupled up substantially to the same
predetermined voltage to inhibit erasing of the shadow memory
block.”

Additionally, neither paragraphs 0030 - 0031 nor any
other passage of the present specification state that the selected
word lines are “likely” to be coupled up to a lower voltage as
alleged by Examiner. The first sentence of paragraph 0031
states in part that “there is the possibility [emphasis added] that
one or more of the unselected word lines nearest the selected
word lines at ground potential might [emphasis added] not have
a high enough voltage to inhibit the erase operation.” There is a
substantial difference between the present specification’s
“possibility” and “might” and Examiner’s “likely”.

The embodiment in which this possibility exists (i.e., the
one or more unselected word lines that do not couple up to a
high enough voltage) is an alternate embodiment that biases the
word lines closest to the selected word lines with a high inhibit
voltage (see paragraph 0031). The Examiner is combining this
alternate embodiment with the embodiment where all of the
unselected word lines have coupled up to the high inhibit
voltage.
(App. Br. 8-10, emphasis added).
The Examiner disagrees:
Claims 9 and 23 stand rejected under 35 U.S.C §]112
first paragraph, because they recite method steps from separate
embodiments (Figure 3 and Figure 4) in a combination not
originally disclosed. That is to say, the methods of claims 9
and 23 constitute new matter.
Claims 9 and 23 recite “wherein preventing further erase
operations comprises biasing each word line of the shadow
memory sub-block at a same voltage that inhibits the erase
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operations ...” Applicant points to paragraph 0029 for support.
Paragraph 0029 directs one of ordinary skill to bias “unselected
word lines ... at some high inhibit voltage.” The unselected
word lines which are biased in this passage are the word lines
making up the sub-block not selected for erasure. Contrarily,
the limitation of “preventing further erase operations ... if a
quantity of program/erase cycles ... is greater than a
predetermined threshold” requires that the sub-block be
selected for erasure before it is determined if a count has been
reached and is biased with the inhibit voltage. Applicant’s
original disclosure fails to support that the word lines of a sub-
block selected for erasure is biased with an erase-inhibit
voltage.
On the last paragraph of page 8 of the Brief, Appellant
agrees with the Examiner’s position that the specification does
not specifically state that “prohibiting” a program/erase
operation is performed by providing “inhibiting” voltages to the
word lines, but argues that “one of ordinary skill in the art upon
reading the present specification could certainly come to the
conclusion that ‘prohibiting’ a program/erase operation can be
accomplished by providing ‘inhibit voltages’.” (emphasis
added). Although the examiner agrees with this assessment of
the level of ordinary skill--it is the basis for the rejection under
35 U.S.C §]103(a)--this argument fails to show that Appellant
possessed the claimed method at the time of filing.
(Ans. 12-13, italics added, underline in original).
New or amended claims which introduce elements or limitations
which are not supported by the as-filed disclosure violate the written
description requirement. See, e.g., In re Lukach, 442 F.2d 967 (CCPA
1971). The purpose of the written description requirement is to prevent an
Applicant from later asserting that he invented that which he did not; the
Applicant for a patent is therefore required “to ‘recount his invention in such
detail that his future claims can be determined to be encompassed within his
original creation.’” Amgen Inc. v. Hoechst Marion Roussel Inc., 314 F.3d
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1313, 1330 (Fed. Cir. 2003) (citing Vas-Cath Inc. v. Mahurkar, 935 F.2d
1555, 1561 (Fed. Cir. 1991)). One shows “possession” by descriptive means
such as words, structures, figures, diagrams, and formulas that fully set forth
the claimed invention. Lockwood v. American Airlines, Inc., 107 F.3d 1565,
1572 (Fed. Cir. 1997).
While there is no in haec verba requirement, newly added claim
limitations must be supported in the specification through express, implicit,
or inherent disclosure. The fundamental factual inquiry is whether the
Specification conveys with reasonable clarity to those skilled in the art that,
as of the filing date sought, Applicant was in possession of the invention as
now claimed. See, e.g., Vas-Cath, Inc., 935 F.2d at 1563-64. When an
explicit limitation in a claim is not present in the written description it must
be shown that a person of ordinary skill would have understood that the
description requires that limitation. Hyatt v. Boone, 146 F.3d 1348, 1353
(Fed. Cir. 1998).
Here, the Examiner has rejected claims 9 and 23 under the written
description requirement (§112, first paragraph), “because they recite method
steps from separate embodiments (Figure 3 and Figure 4) in a combination
not originally disclosed.” (Ans. 12-13, emphasis added).
We agree with the Examiner (Ans. 13) that a description which
merely renders obvious the invention for which the benefit of an earlier date
is sought is not sufficient to satisfy the written description requirement. See
Lockwood, 107 F.3d at 1572. 2 We also observe that the Examiner agrees

2 Cf. “Combining two embodiments disclosed adjacent to each other in a
prior art patent does not require a leap of inventiveness.” Boston Scientific
Scimed, Inc. v. Cordis Corp., 554 F.3d 982, 991 (Fed. Cir. 2009).
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with Appellant’s assessment regarding the level of ordinary skill. (Ans. 13,
last paragraph). However, “i]t is not sufficient for purposes of the written
description requirement of § 112 that the disclosure, when combined with the
knowledge in the art, would lead one to speculate as to modifications that
the inventor might have envisioned, but failed to disclose.” Lockwood, 107
F.3d at 1572.
Nevertheless, the issue of written description support in this appeal
presents a close question. In reviewing the originally-filed Specification,
including the claims, we conclude that Appellant’s claimed limitations of :
(1) “preventing further erase operations only on the shadow memory sub-
block if a quantity of program/erase cycles performed on the shadow
memory sub-block is greater than a predetermined threshold,” 3 and (2)
“wherein preventing further erase operations comprises biasing each word
line of the shadow memory sub-block at a same voltage that inhibits the
erase operations” (claims 9 and 23, emphasis added) cover a broader scope
of subject matter than disclosed in the Specification, (i.e., by covering only
two associated embodiments, instead of three or more disclosed
embodiments). Therefore, we apply the guidance of our reviewing court:
However, a patent claim is not necessarily invalid for lack of
written description just because it is broader than the specific
examples disclosed. See Bilstad v. Wakalopulos, 386 F.3d
1116, 1123 (Fed.Cir.2004) (“ ‘We cannot agree with the broad
proposition ... that in every case where the description of the
invention in the specification is narrower than that in the claim

3 This first limitation has some support in originally-filed claim 9:
“preventing further erase operations on the second subset of memory cells if
the quantity of program/erase cycles is greater than a predetermined
threshold;” (Spec. 11).
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there has been a failure to fulfill the description requirement in
section 112.’ ” (quoting In re Smythe, 480 F.2d 1376, 1382
(CCPA 1973))); In re Rasmussen, 650 F.2d 1212, 1215 (CCPA
1981) (explaining that, in the context of written description, the
fact “that a claim may be broader than the specific embodiment
disclosed in a specification is in itself of no moment”); see also
Tex. Instruments, Inc. v. Int’l Trade Comm’n, 805 F.2d 1558,
1563 (Fed.Cir.1986) (“This court has cautioned against limiting
the claimed invention to preferred embodiments or specific
examples in the specification.”).

Martek Biosciences Corp. v. Nutrinova, Inc., 579 F.3d 1363, 1371 (Fed. Cir.
2009).

Here, given the multiple embodiments (> 2) described in paragraphs
0025] - 0031] of Appellant’s Specification, and given the subset of these
multiple embodiments claimed in association (claims 9 and 23), we
cannot agree with Examiner’s finding that there has been a failure to fulfill
the written description requirement because two disclosed embodiments are
claimed in combination.
We also agree with Appellant’s contention that an artisan reading the
Specification would have understood that “[p]rohibiting erase of memory
cells has the same physical result as inhibiting erase of memory cells, i.e.,
the memory cells are not erased.” (App. Br. 9, first paragraph, last
sentence). We further find an artisan reading Appellant’s Specification
would have understood that preventing the erasure of a particular block or
sub-block of memory cells would require the associated word lines to be
biased at some critical voltage (i.e., same voltage) that inhibits the erase
operation.
For these reasons, we find that Appellant’s Specification conveys with
reasonable clarity to those skilled in the art that, as of the filing date sought,
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applicant was in possession of the invention as now claimed. See Vas-Cath,
Inc., 935 F.2d at 1563-64. Therefore, we reverse the Examiner’s written
description rejection of independent claim 9, and associated dependent claim
12, and independent claim 23, and associated dependent claim 24, and also
claims 25, 28, 30, 31, and 34-37 under 35 U.S.C. §112, first paragraph.
Grouping of Claims
Regarding the rejection under §103, Appellant has argued the
obviousness rejections of claims 9 and 23 as a single group. We select
independent claim 9 as the representative claim for this group. See 37
C.F.R. § 41.37(c)(1)(vii). We address claim 25 separately, infra.
Independent Claim 9 - § 103 rejection
Issue: Under § 103, did the Examiner err in finding that the
cited references, either alone or in combination, would have taught or
suggested:
preventing further erase operations only on the shadow
memory sub-block if a quantity of program/erase cycles
performed on the shadow memory sub-block is greater than a
predetermined threshold, wherein preventing further erase
operations comprises biasing each word line of the shadow
memory sub-block at a same voltage that inhibits the erase
operations,]

within the meaning of independent claim 9 (emphasis added)?
Appellant contends that Hosono teaches “a floating state with
different ‘erase inhibition voltages’” (App. Br. 12, line 2). Appellant points
to Chen as teaching (col. 4, lines 18 – 30) “when a block reaches a preset
limit of erase/write cycles, it is mapped out of the system in favor of a
redundant block.” (App. Br. 12). Thus, Appellant contends:
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The combination of Hosono and Chen et al. would map
out the non-selected sub-block when the preset limit of
erase/write cycles had been reached. In the alternative, even if
the mapping out of the block in Chen et al. was ignored, the
combination of Hosono and Chen et al. at best discloses biasing
the word lines of the memory block not being erased with
different voltages. The combination of Hosono with Chen et al.
thus neither teaches nor suggests Appellant’s method for
erasing a memory device that includes “preventing further erase
operations only on the shadow memory sub-block if a quantity
of program/erase cycles performed on the shadow memory sub-
block is greater than a predetermined threshold, wherein
preventing further erase operations comprises biasing each
word line of the shadow memory sub-block at a same voltage
that inhibits the erase operations;” of claims 9 and 23.
(App. Br. 12).
However, the Examiner (Ans. 6) points out that Chen expressly
teaches “[w]hen the cycle count of a block reaches a pre-set limit of
expected endurance, that block can be mapped out of the system in favor of
a redundant block.” (Chen, col. 4, ll. 28-30). We also agree with the
Examiner (Ans. 14) that at least paragraph [0060] of Hosono would have
taught or suggested “wherein preventing further erase operations comprises
biasing each word line of the shadow memory sub-block at a same voltage
that inhibits the erase operations” (Claim 9, emphasis added). We observe
that Hosono expressly teaches that “the entire word lines WL4-WL7 in the
non-selected pages become to have a substantially identical erase-inhibition
voltage in the erase time shown in FIG. 7.” (Hosono, col. 4, para. [0060],
emphasis added).
Thus, we find the evidence supports the Examiner’s responsive
arguments as articulated on pages 14-15 of the Answer. On this record, we
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agree with the Examiner’s underlying factual findings and ultimate legal
conclusion of obviousness regarding representative claim 9. Therefore, we
sustain the Examiner’s obviousness rejection of representative independent
claim 9. Independent claim 23 (not separately argued) falls therewith . See
37 C.F.R. § 41.37(c)(1)(vii).
Independent Claim 25
Regarding independent claim 25, Appellant contends:
The addition of Appellant’s AP A and Miyamoto et al. do
not fix the deficiencies of Hosono and Chen et al. Appellant’s
APA discloses, at paragraph 0008 of the present specification,
that the tub and the source can be biased at 20V during an erase
operation. Miyamoto et at. disclose that both the well substrate
W the source S are biased at 18V during an erase operation.
Neither Miyamoto et at. nor Appellant’s APA disclose “floating
word lines of the shadow memory block such that all word lines
of the shadow memory block are coupled up substantially to the
same predetermined voltage to inhibit erasing of the shadow
memory block” as claimed in Appellant’s claim 25.
(App. Br. 12-13).
However, we agree with the Examiner’s findings and ultimate legal
conclusion of obviousness for claim 25:
As outlined in the rejection, Hosono teaches the memory block
world lines are set to be floating (see paragraphs 0057, “WL4 ...
and WL5-WL7 are set at a floating state”) and are coupled up
(see paragraph 0059, “WL4-WL7 are boosted by capacitive
coupling”) to substantially the same voltage in order to inhibit
erasing (see paragraph 0060, WL4-WL7 ... become to have a
substantially identical erase-inhibition voltage).
(Ans. 16).

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Appellant, who did not file a Reply Brief, has not addressed this
specific reasoning of the Examiner, let alone demonstrated error by the
Examiner, as required to satisfy the burden on appeal with respect to this
ground of rejection. Cf. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI
2010) (precedential). Therefore, for the same reasons articulated by the
Examiner (Ans. 16), we sustain the Examiner’s obviousness rejection of
representative independent claim 25.

Remaining dependent claims 12, 24, 28, 30, 31, and 34-37
Appellant contends that “for all the reasons stated above with respect
to independent claims 9, 23, and 25, the dependent claims are also
allowable.” (App. Br. 13). However, because we did not find Appellant’s
arguments persuasive for independent claims 9, 23, and 25, we sustain the
Examiner’s rejections under §103 for dependent claims 12, 24, 28, 30, 31,
and 34-37, for the same reasons discussed above regarding independent
claims 9, 23, and 25.

DECISION
We reverse the Examiner’s § 112, first paragraph written description
rejection of claims 9, 12, 23-25, 28, 30, 31 and 34-37.
We affirm the Examiner’s obviousness rejections of claims 9, 12, 23-
25, 28, 30, 31, and 34-37.
Because we have affirmed at least one ground of rejection with
respect to each claim on appeal, the Examiner’s decision is affirmed.
See 37 C.F.R. § 41.50(a)(1).

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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(f).

ORDER
AFFIRMED

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