Ex Parte Rodriguez

Patent Trial and Appeal Board

May 31, 2016

12973187 (P.T.A.B. May. 31, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/973, 187 12/20/2010
23494 7590 06/02/2016
TEXAS INSTRUMENTS IN CORPORA TED
P 0 BOX 655474, MIS 3999
DALLAS, TX 75265
FIRST NAMED INVENTOR
John Rodriguez
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
TI-38640.2 1409
EXAMINER
TRAN, ANTHAN
ART UNIT PAPER NUMBER
2825
NOTIFICATION DATE DELIVERY MODE
06/02/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
uspto@ti.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JOHN RODRIGUEZ
Appeal2014-009227
Application 12/973, 187
Technology Center 2800
Before GEORGE C. BEST, N. WHITNEY WILSON, and
JULIA HEANEY, Administrative Patent Judges.
HEANEY, Administrative Patent Judge.
DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Second Non-
Final Rejection2 rejecting claims 1and2 of Application 12/973,187. We
have jurisdiction under 35 U.S.C. § 6(b). We affirm.
1 Appellant identifies the real party in interest as Texas Instruments Inc.
App. Br. 3.
2 Non-Final Rejection mailed September 18, 2013 (hereinafter "Non-Final
Act.")
Appeal2014-009227
Application 12/973, 187
BACKGROUND
The subject matter on appeal relates to a ferroelectric random access
memory (FRAM), comprising a control circuit that writes ferroelectric
capacitors in the FRAM to a preferred data state before packaging of the
FRAM. As a result of setting the capacitors to a preferred data state before
packaging, imprint on the FRAM is reduced. Specification i-fi-1 4, 6-7.
Claim 1 is illustrative and reproduced from the Claims Appendix of
the Appeal Brief as follows (emphasis added):
25. A ferroelectric random access memory (FRAM) array,
compnsmg:
a plurality of electrically conducive bit lines;
a plurality of electrically conducive plate lines, wherein the
plurality of electrically conducive plate lines are substantially
perpendicular to the plurality of electrically conducive bit lines;
a plurality of electrically conducive word lines, wherein the
plurality of electrically conducive word lines are substantially
perpendicular to the plurality of electrically conducive bit lines;
a plurality of transistors electrically coupled to the plurality of
plate lines and the word lines;
at least one reference voltage source coupled to the plurality of
electrically conducive bit lines;
a plurality of sense amplifiers coupled to the plurality of
electrically conducive bit lines and to the at least one reference
voltage source;
a plurality of ferroelectric capacitors coupled to the plurality of
plate lines and to the plurality of plurality of transistors,
wherein the plurality of ferroelectric capacitors store a plurality
of data states; and
a control circuit coupled to the plurality of ferroelectric
capacitors, wherein the control circuit writes the plurality of
ferroelectric capacitors to a preferred data state, using normal
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Appeal2014-009227
Application 12/973, 187
operating voltages, be.fore packaging of the FRAM memory
array;
further wherein a plurality of ferroelectric memory cells
forming the FRAM memory array are allowed to freely change
stored written data states after the packaging of the FRAM
memory array.
REFERENCES
The Examiner relied upon the following prior art in rejecting the
claims on appeal:
Yamada et al., US2006/0114709 June 1, 2006
(hereinafter "Yamada")
Shuto US 6,335,876 Bl Jan. 01, 2002
(hereinafter "Shuto")
THE REJECTION
Claims 1 and 2 are rejected under 35 U.S.C. § 103(a) as unpatentable
over Yamada and Shuto.
DISCUSSION
We have considered each of Appellant's arguments for patentability.
We are not persuaded, however, that Appellant identifies reversible error in
the rejection of claims 1 and 2 under§ 103(a). Accordingly, we affirm the
rejection for the reasons expressed in the Second Non-Final Rejection,
Answer, and below.
Yamada discloses a ferroelectric memory device that stores a plurality
of bits in a single memory cell. Yamada i-f 10. Yamada teaches writing data
to ferroelectric capacitors before packaging, using one time program
("OTP") memory. Id., Fig. 3, i-fi-136-40. The Examiner acknowledges that
Yamada does not disclose that ferroelectric memory cells "are allowed to
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Appeal2014-009227
Application 12/973, 187
freely change stored written data states after the packaging of the FRAM
memory array," but finds that "the idea of performing a writing operation
again after packing to change the previous stored data is well known in the
art." Ans. 4--5. The Examiner thus determines that in view of Shuto' s
disclosure of writing after packaging, it would have been obvious to a person
of ordinary skill to write to the memory again in order to allow a user to
change data after packaging. Non-Final Act. 3--4; Ans. 5 (citing Shuto 1: 12-
18; Fig. 13).
Appellant argues that Yamada does not disclose writing to a preferred
data state before packaging as recited in claim 1. Br. 8. Appellant points to
two embodiments disclosed in Yamada, the third and fifth embodiments, and
argues that because Yamada' s third embodiment stores a file which does not
need rewriting in an OTP memory region, while also storing a file which can
be rewritten in a RAM region (citing Yamada i-fi-1 67---68), therefore
Yamada's fifth embodiment shown in Figs. 12A-12C does not write before
packaging. Br. 8. Appellant's argument is not persuasive because it mixes
different embodiments of Yamada that describe different devices. Id.
Moreover, Appellant does not respond to the Examiner's finding that
Yamada i-fi-1 39--40 explicitly discloses that data is written before packaging.
Br. 7-9.
Appellant further argues that Yamada does not teach that memory
cells are allowed to "freely change stored written data states after the
packaging." Br. 8. The Examiner relies on Shuto for that teaching,
however. Non-Final Act. 3--4; Ans. 5 (citing Shuto 1:12-18; Fig. 13).
Appellant's arguments against Shuto also lack persuasive merit because they
are based on mischaracterization of its teaching. Br. 9. The portion of Shuto
that Appellant contends teaches away from the claimed invention (Shuto
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Appeal2014-009227
Application 12/973, 187
1 :25-30) discloses a problem in the prior art which is the same problem to
which Appellant's Specification is directed (e.g., Spec. i-fi-14, 45), and thus
does not teach away. Further, Appellant's argument that Shuto does not
teach the claimed subject matter because it is directed to "remanent
polarization of memory" (Br. 9 (citing Shuto 1 :42---65)) ignores the fact that
a person of ordinary skill in the art would have understood remanent
polarization loss as the same problem as "imprint," the term used in
Appellant's Specification. See e.g., U.S. Pat. No. 5,740,100 ("Yoo") at
1 :22-24 ("In extreme cases, remanent polarization loss or polarization
reversal occurs, which is known as "imprint.")
Claim 2 depends from claim 1 and recites the additional limitation
that the "preferred data state is a high data state." Appellant argues that
Yamada does not disclose writing to a high data state before packaging
because Yamada i1 45 describes "the signal difference of the initializing
voltages that are used to create an OTP memory that cannot meet the
requirement" of claim 2. Br. 9. Appellant has not explained why Yamada
i145 would not meet claim 2, nor has Appellant responded to the Examiner's
finding that the high data state in Yamada i145 is "1." Thus, we are not
persuaded of reversible error in the Examiner's determination of
unpatentability of claim 2.
SUMMARY
We affirm the rejection of claims 1 and 2.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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