Ex Parte Rivoir

Patent Trial and Appeal Board

Oct 31, 2012

10446568 (P.T.A.B. Oct. 31, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD

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Ex parte JOCHEN RIVOIR
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Appeal 2010-006283
Application 10/446,568
Technology Center 2600
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Before MAHSHID D. SAADAT, DEBRA K. STEPHENS,
and MICHAEL J. STRAUSS, Administrative Patent Judges.

PER CURIAM.

DECISION ON APPEAL

Appeal 2010-006283
Application 10/446,568

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Appellant appeals under 35 U.S.C. § 134(a) from the Final Rejection
of claims 1 and 6-13. Claims 3-5 have been indicated as allowable and
claim 2 has been canceled. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

STATEMENT OF THE CASE
Introduction
Appellant’s invention relates to adjustment of transitions within a bit
stream based on a pattern matching algorithm for comparing the received bit
stream with the expected bit stream (see Spec. 2:4-15, 25-28).
Exemplary Claim
Independent claim 1 is exemplary of the claims under appeal and
reads as follows:
1. A method for adjusting transitions in a bit stream
of a signal to be evaluated by comparison with a predetermined
expected bit stream, comprising the steps of:
receiving said bit stream by a transition adjustment filter,
providing a transition frame signal to said transition
adjustment filter, said transition frame signal providing
information for eliminating non-deterministic clock latencies
within said bit stream of said received signal, and
adjusting said bit stream of said received signal
according to said transition frame signal resulting in an adjusted
bit stream being in alignment to the predetermined expected bit
stream.
Rejection on Appeal
The Examiner rejected claims 1 and 6-13 under 35 U.S.C. § 102(e) as
being anticipated by Klotchkov (US 2003/0208717 A1).
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Appellant’s Contentions
With respect to claim 1, Appellant contends that, rather than adjusting
transitions in a bit stream according to transition frame signal, Klotchkov
adjusts skew between bit streams in response to calibrated register clock
signals (App. Br. 9-10). Appellant further asserts that the Examiner’s
characterization of the delay Td as a register clock is in error because
paragraphs 91-95 of Klotchkov do not teach the claimed “transition frame
signal providing information for eliminating non-deterministic clock
latencies” because “Td is an ‘actual value of signal delay’ between an edge
of a ‘main clock’ and the ‘moment when the register actually latches input
data’” (App. Br. 10). Appellant explains that such programmed delay will
affect every transition of a clock signal and therefore, the delay Td “is not a
frame signal, as there are no bits being ‘framed’” (id). Additionally,
Appellant relies on pages 2 and 6 of the instant Specification for defining a
transition frame signal as a signal that frames “blocks of bits” (App. Br. 10-
11) and argues that “Klotchkov’s delay value and register clocks adjust the
skew of an entire bit stream, and do not eliminate ‘non-deterministic clock
latencies within [a] bit stream” (App. Br. 11).
Appellant further argues the patentability of claims 6-13 based on the
same reasons presented for claim 1, allowing these claims to fall with
representative claim 1 (id.).

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellant’s
arguments that the Examiner has erred. We disagree with Appellant’s
conclusion. We adopt as our own (1) the findings and reasons set forth by
Appeal 2010-006283
Application 10/446,568

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the Examiner in the action from which this appeal is taken and (2) the
rebuttals to arguments expressed by the Examiner in the Examiner’s Answer
in response to Appellants’ Appeal Brief (see Ans. 15-16).
We specifically agree with the Examiner (Ans. 12-13), that paragraph
96 of Klotchkov describes the ways the non-deterministic latency as the
uncertainty in determining the signal delay may be overcome and corrected.
Klotchkov uses the signal delay Td to compensate for the time differences
between when the register latches input data and the reference clock edge (¶
[0091]). As further explained by the Examiner, the claim recites “a
transition frame signal” for providing information related to time locations
of non-deterministic latencies, which is met by the register clock of
Klotchkov having delay time information for eliminating the non-
deterministic latencies by compensating for the time differences (see Ans. 13
(citing Klotchkov, ¶¶ [0091] – [0096]).
Contrary to Appellant’s assertion (App. Br. 10-11, Reply Br. 2-3), the
claim does not preclude framing a bit segment by a signal, such as
Klotchkov’s register clock signal, as the transition frame signal. In fact,
similar to Appellant’s frame signal, this register clock signal in Figure 5
provides information regarding the length and the alignment of bit segments
and therefore, frames “blocks of bits.” Furthermore, we find the Examiner
properly concludes that, by determining the signal delay Td, the received bit
stream or the data output is adjusted and aligned to “the predetermined
expected bit stream” or the expected data (see Ans. 13-14 (citing Klotchkov,
¶ [0005])).

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Application 10/446,568

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CONCLUSIONS
1. The Examiner has not erred in rejecting claims 1 and 6-13
under 35 U.S.C. § 102(e) as being anticipated by Klotchkov.
2. Claims 1 and 6-13 are not patentable.

DECISION
The Examiner’s decision rejecting claims 1 and 6-13 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

ELD