Ex Parte Ricketts et al

Patent Trial and Appeal Board

May 30, 2018

13918786 (P.T.A.B. May. 30, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/918,786 06/14/2013 Scott Ricketts
75359 7590 06/01/2018
ZILKA-KOTAB, PC-NVID
1155 N. 1st St.
Suite 105
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
NVIDP848/SC-12-0715-US1 1083
EXAMINER
WEI,JANE
SAN JOSE, CA 95112 ARTUNIT PAPER NUMBER
2131
NOTIFICATION DATE DELIVERY MODE
06/01/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
zk-uspto@zilkakotab.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SCOTT RICKETTS, NICHOLAS WANG,
SHIRISH GADRE, GENTARO HIROTA, and
ROBERT JR. OHANNESSIAN
Appeal 2017-011203
Application 13/918,786 1
Technology Center 2100
Before ERIC B. CHEN, KARA L. SZPONDOWSKI, and
PHILLIP A. BENNETT, Administrative Patent Judges.
BENNETT, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's final
rejection of claims 1--4, 6-16, and 18-22. We have jurisdiction under
35 U.S.C. § 6(b).
We reverse.
1 Appellants' Brief ("App. Br.") identifies NVIDIA Corporation as the real
party in interest. App. Br. 3.
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Application 13/918,786
CLAIMED SUBJECT MATTER
The claims are directed to reducing latency when processing tasks are
selected for execution in parallel processors by generating a cache warming
instruction which is executed by the processor to load program instructions
into cache prior to launching the processing task. Spec. ,r 15. Claim 1,
reproduced below, is illustrative of the claimed subject matter:
1. A method comprising:
receiving, by a task management unit within a parallel
processor, a task data structure that defines a processing task;
extracting information stored in a cache warming field of
the task data structure; and
generating, by the task management unit prior to execution
of the processing task by a processing core within the parallel
processor, a cache warming instruction that is configured to load
one or more entries of a cache storage with data fetched from a
memory when executed by the processing core.
App. Br. 22 (Claims Appendix).
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Vanzante
Purcell
Frank
Hooker
Aikawa
Shiell
US 2008/0104322 Al
US 2013/0074088 Al
US 2012/0110269 Al
US 2004/0260877 Al
us 5,371,865
us 6,119,222
2
May 1, 2008
Mar. 21, 2013
May 3, 2012
Dec. 23, 2004
Dec. 6, 1994
Sep. 12,2000
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Application 13/918,786
REJECTIONS
Claims 1--4, 6, 13-16, 18 and 20-22 stand rejected under 35 U.S.C.
§ 103 as being unpatentable over Purcell and Vanzante. Final Act. 2-14.
Claims 7, 8, and 19 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Purcell, Vanzante, and Aikawa. Final Act. 14--17.
Claim 9 stands rejected under 35 U.S.C. § 103 as being unpatentable
over Purcell, Vanzante, and Shiell. Final Act. 17-18.
Claims 10 and 11 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Purcell, Vanzante, and Frank. Final Act. 18-21.
Claim 12 stands rejected under 35 U.S.C. § 103 as being unpatentable
over Purcell, Vanzante, and Hooker. Final Act. 21-22.
ISSUE
Has the Examiner erred in finding Purcell teaches or suggests
"generating, by the task management unit prior to execution of the
processing task by a processing core within the parallel processor, a cache
warming instruction that is configured to load one or more entries of a cache
storage with data fetched from a memory when executed by the processing
core," ("the disputed limitation") as recited in claim 1 ?2
2 Appellants raise additional issues for consideration in their briefs.
However, because this issue is dispositive of the rejections on appeal, we do
not address the remaining issues raised therein.
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Application 13/918,786
ANALYSIS
In rejecting claim 1, the Examiner finds Purcell teaches all limitations
of the claim except for "how the loading of the one or more entries of a
cache is initiated." Final Act. 4. The Examiner further finds Vanzante cures
this deficiency because it teaches the generation of cache warming
instructions that populate cache entries with data fetched from memory.
Final Act. 4 (citing Vanzante Fig. 4, ,r,r 26, 72). Relevant to the issue before
us, the Examiner finds Purcell teaches the disputed limitation because it
teaches a task management unit that schedules processing tasks for
execution by general processing clusters and utilizes a QMD (queue
metadata) cache to store program instructions for those processing tasks.
Final Act. 3--4. The Examiner explains:
While referring to a processor, an instruction is a segment of code
that contains steps that need to be executed by the processor. For
a processor to do something, instructions have to be given to the
processor so it knows how to do what it is being asked to do ....
In order for the task management unit to perform loading data
into a cache, the task management unit must generate an
instruction that instructs the unit to load data into a cache such
that the processor can execute the instruction.
Ans. 7.
Appellants argue the Examiner has erred because Purcell fails to teach
or suggest that any unit within the parallel processor generates a cache
warming instruction (or any other instruction) that is executed by the general
processing clusters in the parallel processor. App. Br. 14. Addressing the
Examiner's finding that Purcell's task management unit must generate an
instruction, Appellants contend Purcell merely teaches that QMD ( queue
metadata) 622 is fetched from parallel processing memory 204, but "fails to
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Application 13/918,786
teach or suggest that an instruction is generated by the task management unit
to 'fetch' the remainder of the QMD 622 from memory." Reply Br. 5 (citing
Purcell ,r 68). Appellants further argue Purcell teaches that loading the
QMD cache 605 occurs without the need for any generated instruction by
the task management unit. In particular, Appellants argue that an entry in
the QMD cache is loaded only in response to a cache miss. Reply Br. 5
( citing Purcell ,r 71 ). Appellants also contend the Examiner has failed to
show the cache is loaded when the cache warming instruction is executed by
the processing core because it teaches the task management unit 600, and not
the GPCs 208, write the data to the cache. App. Br. 13.
In order for Purcell to teach the disputed limitation, the task/work unit
207, and more precisely the task management unit 300 within task/work unit
207, needs to be the component in Purcell's system that generates a cache
warming instruction, and that the generated instruction needs to be received
and executed by the GPCs 208 in processing cluster array 230. We agree
with Appellants that the Examiner has failed to identify sufficient evidence
that this is the case.
The Examiner finds Purcell's loading of QMD 622 into QMD cache
605 by task management unit 600 corresponds to the recited "generating, by
the task management unit ... a cache warming instruction that is configured
to load one or more entries of a cache storage with data fetched from a
memory when executed by the processing core," and that because the task
management unit performs the loading, it must necessarily generate the
instruction to do so. We discern two problems with these findings.
First, the claim recites that the cache warming instruction is "executed
by the processing core." App. Br. 22 (Claims Appendix). The Examiner
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identifies Purcell's general processing clusters 208 ("GPC' s") as
corresponding to the recited "processing core." Final Act. 3. The Examiner
does not sufficiently explain, however, how Purcell teaches that the cache
warming instruction is executed by those same GPC' s, an explanation
necessary to support the Examiner's finding that the cache warming
instruction is "executed by the processing core."
Second, we agree with Appellants' argument that Purcell does not
teach the parallel processor component generates any instruction to load a
portion of the QMD into the QMD cache. In discussing the implementation
of QMDs and the use of the QMD cache, Purcell states that "[t]he QMDs are
written under software control," (Purcell ,r 69) and that "[t]he portion of
AMD 622 that can be accessed by software is typically filled by software to
initiated a task." Id. These statements indicate, at least, that the instruction
to write to the QMD cache is not necessarily generated by the task
management unit as the Examiner finds, and they tend to demonstrate the
instruction is generated instead by software.
The description of the process for loading an entry in the QMD cache
further supports Appellants' argument, as it indicates "the [ Q MD cache]
entry may be identified in response to a cache miss." Purcell ,r 71. Thus,
although Purcell teaches the task management unit performs the copying of
the QMD into the QMD cache, it does not teach the instruction to do so is
generated by the task management unit as required by Appellants' claims.
Accordingly, we do not sustain the rejection of claim 1 under 35 U.S.C.
§ 103. For the same reasons, we do not sustain the rejections of independent
claims 13 and 20, which recite substantially similar features. The remaining
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claims depend from one of the independent claims, and therefore stand with
their respective independent claim.
DECISION
We reverse the Examiner's rejections of claims 1--4, 6-16, and 18-22.
REVERSED
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