Ex Parte Richter

Patent Trial and Appeal Board

Feb 1, 2017

12871348 (P.T.A.B. Feb. 1, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/871,348 08/30/2010 Matthias Richter INF 2010 P 50763 US 1581
48154 7590
SLATER MATSIL, LLP
17950 PRESTON ROAD
SUITE 1000
DALLAS, TX 75252
EXAMINER
GAMI, TEJAL
ART UNIT PAPER NUMBER
2126
NOTIFICATION DATE DELIVERY MODE
02/03/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing @ slatermatsil. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MATTHIAS RICHTER
Appeal 2016-006422
Application 12/871,348
Technology Center 2100
Before STEPHEN C. SIU, ERIC S. FRAHM, and JOHN D. HAMANN,
Administrative Patent Judges.
SIU, Administrative Patent Judge
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) from the
Examiner’s Final Rejection of claims 1—4, 10—12, and 14—30. We have
jurisdiction under 35 U.S.C. § 6(b).
The disclosed invention relates generally to a semiconductor
fabrication process. Spec 1. Independent claims 1 and 17 read as follows
1. A method for controlling a semiconductor
manufacturing process of a plurality of structured production
wafers, the method comprising:
forming the plurality of structured production wafers
using the semiconductor manufacturing process, wherein each
of the plurality of structured production wafers comprise a
plurality of dies in production;
Appeal 2016-006422
Application 12/871,348
taking a series of images of the plurality of structured
production wafers, wherein one image is taken for each
structured production wafer, and wherein the image is taken of
the same location for each structured production wafer;
generating a series of histograms, each histogram
generated from a corresponding image;
selecting information from each histogram, the
information being based on at least one of a number of peaks, a
grey level peak 1, a peak 1 width, a peak 1 value, a grey level
peak 2, a peak 2 width, or a peak 2 value;
monitoring the information;
controlling the semiconductor manufacturing process by
adjusting or shutting down the semiconductor manufacturing
process if the information violates a predefined threshold value;
and
processing another batch of structured production wafers
using the semiconductor manufacturing process if the
information does not violate the predefined threshold value.
17. A method comprising:
selecting a first die location on a first structured wafer
comprising a first plurality of dies;
taking a first image of the first die location;
generating a first histogram from the first image;
selecting first information from the first histogram, the
first information being based on at least one of a number of
peaks, a grey level peak 1, a peak 1 width, a peak 1 value, a
grey level peak 2, a peak 2 width, or a peak 2 value for each
histogram;
selecting a second die location on a second structured
wafer, wherein the first die location comprises a same
coordinate as the second die location;
taking a second image of the second die location;
generating a second histogram from the second image;
selecting second information from the second histogram,
the second information being based on at least one of the
number of peaks, the grey level peak 1, the peak 1 width, the
peak 1 value, the grey level peak 2, the peak 2 width, or the
peak 2 value for each histogram; and
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Application 12/871,348
comparing the first information and the second
information.
The Examiner rejects claims 17—20, 22, and 27 under 35 U.S.C.
§ 102(b) as anticipated by Smith et al. (US 2005/0132306 Al, published
June 16, 2005); claims 1—4, 11, 12, 14, 16, 23—26, and 28—30 under 35
U.S.C. § 103(a) as unpatentable over Smith and Paik (US 6,961,626 Bl,
issued November 1, 2005); and claims 10, 15, and 21 under 35 U.S.C.
§ 103(a) as unpatentable over Smith, Paik, and Takafuji et al. (US
2006/0022295 Al, published February 2, 2006).
ISSUE
Did the Examiner err in rejecting claims 1—4, 10—12, and 14—30?
ANALYSIS
Claims 17—20, 22, and 27 — anticipation (Smith)
Claim 17 recites selecting a first die location on a first structured
wafer and taking a first image of the first die location. The Examiner states
that Smith discloses this feature. Final Act. 2—3 (citing Smith H 22, 42,
515, Figs. 13B, 59A, 66B, 108B). We agree with the Examiner. For
example, as the Examiner points out, Smith discloses determining “which
sites or location” in a “particular chip or die” (i.e., selecting a die location, as
recited in claim 17) and measuring a die that is selected “from among the
multiple dies across the wafer” (i.e., the “die” is a location on a “wafer,” as
recited in claim 17). Smith 122. Smith also discloses that this process may
include the display (or “taking”) chip images (i.e., “a first image”). Smith
142.
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Appellant cites to various portions of the Smith reference as using the
term “predict,” “predicting,” or “prediction,” and disclosure of various
actions performed “before processing of the new IC design” and “without
actually developing expensive lithography masks and processing the new IC
design.” Appellant argues that Smith merely discloses “the use of test
wafers” in which various actions are performed and appears to suggest that
the “test wafer” of Smith is not a “structured wafer,” as recited in claim 17.
App. Br. 15-20 (citing Smith H 22, 42, 313, 515, 522, 552, 682, 703, 704;
Figs. 59A, 66B, 108A). We agree with Appellant that Smith discloses “test
wafers.” Smith || 313, 682. Also, as previously discussed, Smith discloses
selecting a die “from among the multiple dies across the wafer” and taking a
“chip image.” Appellant does not assert or demonstrate persuasively a
difference between the “wafer” or “test wafer” of Smith and the “structured
wafer,” as recited in claim 17. In both cases, a “wafer” is utilized.
Appellant also argues that the disclosure of Smith in which “sites or
locations . . . within a particular chip or die . . . among the multiple dies
across the wafer” “does not teach or suggest” a “structured wafer” because,
according to Appellant, this disclosure of Smith is “from the back ground of
the application” and is, therefore, “not even clear.” App. Br. 17 (citing
Smith 122). We disagree with Appellant’s argument. It would have been
“clear” to one of skill in the art, not being an automaton, that a “wafer” from
which a site or location is selected, as disclosed by Smith, is a (structured)
wafer because Smith provides this explicit disclosure. Appellant does not
explain persuasively why one of skill in the art would have been “unclear”
about whether the known “wafer” of Smith constitutes a “wafer” based on
the location of the disclosure within the Smith reference (i.e., in the
“background” section).
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Claim 17 recites selecting first information from the first histogram,
the first information being based on at least one of a number of peaks, a grey
level peak 1, a peak 1 width, a peak 1 value, a grey level peak 2, a peak 2
width, or a peak 2 value for each histogram. The Examiner states that Smith
discloses this feature. Final Act. 3 (citing Smith Fig. 40). Appellant argues
that Smith fails to disclose this feature because, according to Appellant,
Smith merely discloses “a screenshot of a comparison tool GUI showing
full-chip statistical histogram” that is “used according to [a] framework” in
which “the design team completes a layout, which is then uploaded using a
GUI” and then “provided back to the user (in Figure 30).” App. Br. 20—21
(citing Smith Figs. 28-40; 1114). Hence, Appellant appears to argue that
Smith discloses a GUI but fails to disclose a first histogram, as recited in
claim 17. We agree with Appellant that Smith discloses a GUI. However,
as the Examiner points out, Smith discloses a histogram displayed within the
GUI and also explicitly discloses the use of “statistical histograms.” Smith
Fig. 40,142. Appellant does not assert or explain persuasively a difference
between the histogram or statistical histogram of Smith and the histogram,
as recited in claim 17.
Claim 19 recites a first location and a second location on a wafer
comprise a deep trench. The Examiner finds that Smith discloses a “deep
trench.” Final Act. 4 (citing Smith 1 817). As the Examiner points out,
Smith discloses creating “deep trenches.” Smith 1817. Appellant argues
that Smith fails to disclose a deep trench because, according to Appellant,
Smith merely discloses a process of “creating] deep trenches . . . in . . .
defined . . . areas” but that “the relationship between [creating deep trenches
of Smith] and the claimed limitation [of a deep trench]” is supposedly
“puzzling.” App. Br. 21. We disagree with Appellant’s argument. One of
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skill in the art, not being an automaton, would not have been “puzzled” over
whether there is a relationship between the “deep trench” of Smith and the
“deep trench,” as recited in claim 19. Rather, given that in both cases, a
“deep trench” is described, one of skill in the art would have understood the
“deep trench” of Smith to be the same as the “deep trench,” as recited in
claim 19.
Claim 22 recites controlling or shutting down a semiconductor
manufacturing process if the first or second information violates a
predefined threshold value. The Examiner finds that Smith discloses this
feature. Final Act. 5 (citing Smith 1467). We agree with the Examiner. As
the Examiner points out, Smith discloses that “feature dimensions [are]
produced” on a chip and “match[ed] [to] the dimensions as they were
designed.” If the feature dimensions that were produced do not match (i.e.,
violates a predefined condition or threshold value), the layout and masks are
modified (or controlled) in order “to yield the designed features.” Smith
1467. In other words, Smith discloses producing feature dimensions on a
chip, comparing the feature dimensions on the chip with the previous design
criteria and modifying (or controlling) the process if the feature dimensions
on the chip do not match the previous design criteria (i.e., violates a
predefined threshold value).
Appellant argues that Smith fails to disclose this feature because,
according to Appellant, Smith merely discloses “us[ing] . . . models for
pattern dependent variations . . . [and if] the expected feature size does not
match the designed features size, then either the layout is changed or the
mask is changed” and that “modifying layouts and masks is different from
adjusting ... a semiconductor manufacturing process.” App. Br. 22.
Appellant does not demonstrate persuasively a meaningful difference
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between modifying the layout and mask to yield the designed features in
semiconductor processing, as disclosed by Smith, and “adjusting” a
semiconductor manufacturing process, as recited in claim 17. In both cases,
a semiconductor manufacturing process is modified (or adjusted).
Claim 27, which depends from claim 17, recites that the first die
location comprises a same coordinate as the second die location. The
Examiner finds that Smith discloses this feature. Final Act. 3 (citing Smith
1703). As the Examiner points out, Smith discloses using “one [die] at the
edge of wafer, one at the center of the wafer, and one at some distance in-
between” and measuring these dies “across multiple wafers.” Smith 1703.
Hence, Smith discloses a first die location on one wafer (e.g., a die at the
edge of the wafer) and the same die location on another wafer (i.e.,
measurements of the die “across multiple wafers”). Appellant argues that
Smith fails to disclose “taking an image at the same location on different
wafers.” App. Br. 22—23. However, Appellant does not explain
persuasively a meaningful difference between the disclosure of Smith of
measuring one die location across multiple wafers and the claim feature of a
first and second die location comprising a same coordinate. In both cases,
two die locations on different wafers have the same coordinates (because
they are located at the same location within the respective wafers).
Claims 1^4, 10-12, 14—16, 21, 23—26, and 28—30 —Obviousness
The Examiner finds that it would have been obvious to one of
ordinary skill in the art to have combined the teachings of Smith and Paik in
order to manage “error or some deviation from the intended target result or
specification,” which, according to the Examiner, would have been known to
occur by one of ordinary skill in the art. Final Act. 8.
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Appellant argues that it would not have been obvious to one of skill in
the art to have combined the teachings of Smith and Paik because Smith
discloses “modifying the mask or layout prior to production of wafers” and
Paik discloses “process control during semiconductor manufacturing,” that
“changes in the layout or mask is extremely costly,” and that “there is no
reason to combine [Smith with Paik].” App. Br. 23—24. However, Appellant
does not explain persuasively the supposed flaws in the Examiner’s
proffered rationale for combining the teachings of Smith and Paik. We are
not persuaded by Appellant’s argument.
Claim 1 recites controlling the semiconductor manufacturing process.
Appellant argues that Smith fails to disclose “control of a semiconductor
manufacturing” process and that Smith merely discloses “modifying a
layout, which is generated before the mask is fabricated.” App. Br. 24, 26
(citing Smith 1293). This argument was previously addressed above.
Appellant argues that, in Smith, “it is inconceivable to produce
another batch of wafers if the condition is not met and to produce a new
layout (and associated mask) if the condition is met.” App. Br. 26—27. In
other words, Appellant argues that Smith fails to disclose or suggest
producing a batch of wafers if a condition is not met and producing a new
layout (and associated mask) if the condition is met. Claim 1 recites
controlling the semiconductor manufacturing process by adjusting or
shutting down the semiconductor manufacturing process if the information
violates a predefined threshold value. Appellant does not demonstrate, and
we do not observe, that claim 1 also recites producing a batch of wafers if a
condition is not met and producing a new layout (and associated mask) if the
condition is met. Therefore, we are not persuaded by Appellant’s argument.
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Claim 1 recites a plurality of structured production wafers and that an
image is taken from the same location for each structured production wafer.
Appellant argues that Smith fails to disclose this feature. App. Br. 27.
Appellant provides similar arguments with respect to claim 11. App. Br. 28.
This argument was previously addressed above.
Claim 28 recites structured production wafers. Appellant argues that
Smith discloses “test wafers and not wafers with dies (production wafers) as
in claim 28.” App. Br. 29. This argument was previously addressed above.
Claim 29 recites shutting down the semiconductor manufacturing
process if the information violates a predefined threshold value. The
Examiner finds that Paik discloses this feature. Final Act. 15—16 (citing
Paik 17:5-10).
Appellant argues that Paik fails to disclose shutting down the
semiconductor manufacturing process because, according to Appellant, the
“on/off mechanism” of Paik “relates to the decision as to whether to update
the process control block 201.” App. Br. 29—30 (citing Paik 17:5—10, Fig.
2). Appellant provides similar arguments with respect to claim 30. App. Br.
30.
We agree with the Examiner that it would have been obvious to one of
ordinary skill in the art to have performed a semiconductor manufacturing
process and controlled the process if information violates a predefined
threshold value (or if the results are erroneous or not within normal limits).
“One of the ways in which a patent’s subject matter can be proved obvious
is by noting that there existed at the time of invention a known problem for
which there was an obvious solution encompassed by the patent’s claims.”
KSR Inti Co. v. Teleflex Inc., 550 U.S. 398, 419-20 (2007). In the present
case, it was known to one of ordinary skill in the art, as disclosed by Smith,
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for example, that semiconductor manufacturing process may provide
undesired or incorrect results and that one of ordinary skill in the art would
have responded to such a scenario. Faced with such a semiconductor
manufacturing process that produces undesired or incorrect results, as
disclosed by Smith, one of skill in the art would have responded by selecting
from a finite number of known responses.
In the present case, one of ordinary skill in the art, who is a person of
ordinary skill and ordinary creativity (i.e., “not an automaton” — KSR, 550
U.S. at 420), would have understood that a finite number of predictable
solutions includes either modifying/adjusting the process to provide correct
or desired results, or discontinuing (i.e., “shutting down”) the (erroneous)
process.
When . . . there are a finite number of identified, predictable
solutions, a person of ordinary skill has good reason to pursue
the known options within his or her technical grasp. If this
leads to the anticipated success, it is likely the product not of
innovation but of ordinary skill and common sense. In that
instance the fact that a combination was obvious to try might
show that it was obvious under § 103.
KSR, 550 U.S. at 421. Hence, it at least would have been obvious to one of
ordinary skill in the art to have chosen a predictable solution to a known
problem from a finite list of two predictable solutions (i.e., correct the
problem or discontinue the process). In addition, Appellant has provided no
evidence to show that discontinuing a process (or “shutting down” a process)
that is providing undesired results was “uniquely challenging or difficult for
one of ordinary skill in the art.” See Leapfrog Enters., Inc. v. Fisher-Price,
Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR, 550 U.S. at 418).
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Appellant does not provide additional arguments with respect to the
other claims under appeal or arguments with respect to Takafuji. App. Br.
31.
DECISION
We affirm the Examiner’s rejection of claims 17—20, 22, and 27 under
35 U.S.C. § 102(b) as anticipated by Smith; claims 1—4, 11, 12, 14, 16, 23—
26, and 28—30 under 35 U.S.C. § 103(a) as unpatentable over Smith and
Paik; and claims 10, 15, and 21 under 35 U.S.C. § 103(a) as unpatentable
over Smith, Paik, and Takafuji.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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