Ex Parte Rhodes

Patent Trial and Appeal Board

Jan 28, 2016

12619296 (P.T.A.B. Jan. 28, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/619,296 11/16/2009 Howard E. Rhodes
58907 7590 02/01/2016
ROUND
LERNER, DAVID, LITTENBERG, KRUMHOLZ & MENTLIK, LLP
600 SOUTH A VENUE WEST
WESTFIELD, NJ 07090
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
ROUND 3.0-002 DCCDCII 8343
EXAMINER
MALDONADO, TIJLIO J
ART UNIT PAPER NUMBER
2898
NOTIFICATION DATE DELIVERY MODE
02/01/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
eOfficeAction@ldlkm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte HOWARD E. RHODES
Appeal2013-008694
Application 12/619,296
Technology Center 2800
Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and
JAMES C. HOUSEL, Administrative Patent Judges.
HANLON, Administrative Patent Judge.
DECISION ON APPEAL
A. STATEMENT OF THE CASE
The Appellant filed an appeal under 35 U.S.C. § 134 from a final rejection
of claims 87-96 and 98-111. We have jurisdiction under 35 U.S.C. § 6(b ).
We AFFIRM.
The claims on appeal are directed to a CMOS imager (claims 87-96, 98-
102) and a camera system comprising a CMOS imager (claims 103-111). More
specifically, "the [Appellant's] invention relates to a method for providing a
silicide coating over the transistor gates used in a CMOS imager to improve the
operating speed of the transistors." Spec. 1, 11. 6-8.
According to the Appellant:
Appeal2013-008694
Application 12/619,296
In the prior art, the desire to incorporate a silicide over the gate
stack to improve speed was hampered by the undesirable effect the
silicide layer had on the photo gate. If the photo gate is covered by a
silicide layer, the collection of charge is inhibited by the blocking of
light by the silicide layer. It is for this reason that photogate type
devices have not been able to use a silicide gate stack.
Spec. 10, 11. 1-5.
The Appellant discloses:
a method for providing a more conductive layer, such as a silicide or a
barrier/metal layer, incorporated into the transistor gates of a CMOS
imager to improve the speed of the transistor gates, but selectively
removing the silicide or barrier/metal from a photogate to prevent
blockage of the photo gate.
Spec. 10, 11. 13-17.
Representative claim 87 is reproduced below from the Claims Appendix of
the Appeal Brief dated January 10, 2013 ("App. Br."). The limitation at issue is
italicized.
87. A CMOS imager, comprising:
an array of pixels, at least one pixel comprising:
a photo-collection region to accumulate photo-generated
charge, wherein a silicide layer is substantially not formed on a
surface of the photo-collection region; and
a transfer transistor to transfer the charge from the photo-
collection region to a floating diffusion node, wherein the transfer
transistor includes a polysilicon transfer gate upon which the silicide
layer is formed and remains, and the floating diffusion node upon
which the silicide layer is first formed and then substantially removed.
App. Br. 23 (emphasis added).
The Appellant seeks review of the following rejections: 1
1 The Appellant also requests that the Examiner's requirement for a supplemental
oath or declaration under 37 C.F.R. § 1.67 be withdrawn. App. Br. 5-10. This
2
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Application 12/619,296
(1) claims 87-96 and 98-102 under 35 U.S.C. § 112, first paragraph, as
failing to comply with the written description requirement;
(2) claims 87-90, 94, 95, and 98 under 35 U.S.C. § 103(a) as
unpatentable over the combination of the admitted prior art, 2 Fossum, 3 Park, 4 and
Merri11· 5
'
(3) claims 91-93 and 96 under 35 U.S.C. § 103(a) as unpatentable over
the combination of the admitted prior art, Fossum, Park, and Merrill, and further in
view of Schwalke6 or Watanabe; 7
(4) claims 99-102 under 35 U.S.C. § 103(a) as unpatentable over the
combination of the admitted prior art, Fossum, Park, and Merrill, and further in
view of Kusaka; 8
(5) claims 103-105 and 109-111under35 U.S.C. § 103(a) as
unpatentable over the combination of the admitted prior art, Fossum, Park, Merrill,
and Kusaka; and
(6) claims 106-108 under 35 U.S.C. § 103(a) as unpatentable over the
combination of the admitted prior art, Fossum, Park, Merrill, and Kusaka, and
further in view of Schwalke or Watanabe.
matter is properly raised by a petition under 3 7 C.F .R. § 1.181. MPEP
§ 1002.02(c) (8th ed., Rev. 9, Aug. 2012) ("4. Petitions under 37 CFR 1.113
relating to objections or requirements made by the examiners."). Petitionable
matters are not appealable to the Patent Trial and Appeal Board. MPEP § 1201.
2 Pages 1-9 of the Appellant's Specification and Appellant's Figures 1 and 2
("APA").
3 US 5,471,515, issued November 28, 1995.
4 US 6,040,593, issued March 21, 2000.
5 US 6, 160,282, issued December 12, 2000.
6 US 6,037,196, issued March 14, 2000.
7 US 4,816,424, issued March 28, 1989.
8 US 5,754,224, issued May 19, 1998.
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Application 12/619,296
The rejections are sustained for the reasons set forth in the Final Office
Action dated May 23, 2012 ("Final") and the Examiner's Answer dated April 26,
2013 ("Ans."). We add the following for emphasis.
B. DISCUSSION
1. Rejection (1)
The Examiner finds "[t]here is no support or description regarding the
floating diffusion node upon which the silicide layer is first formed and then
substantially removed" in claim 87. Final 3. The Examiner also finds "[ t ]here is
no support or description regarding the source follower transistor having silicide
gate coupled to floating diffusion node" in claims 90, 99, and 101. Final 3.
Finally, the Examiner finds "[t]here is no support for the reset transistor being
coupled between the floating diffusion node, the reset transistor having silicide
gate" in claims 89, 99 and 101. Final 4.
Claim 87 recites, in relevant part, "[a] CMOS imager, comprising: ... a
photo-collection region ... , wherein a silicide layer is substantially not formed on
a surface of the photo-collection region; and a transfer transistor ... , wherein the
transfer transistor includes a polysilicon transfer gate upon which the silicide layer
is formed and remains, and the floating diffusion node upon which the silicide
layer is first formed and then substantially removed." App. Br. 23 (emphasis
added).
The embodiment depicted in Appellant's Figures 7-11 corresponds to the
CMOS imager recited in claim 87. Appellant's Figure 7, reproduced below,
illustrates a portion of a semiconductor CMOS imager wafer comprising p-well
substrate 310 having n-doped region 316 therein for photocollection and field
oxide regions 341. Spec. 17, 11. 6-15.
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Application 12/619,296
FIG. 7
Appellant's Fig. 7 depicts a partially cut away side view
of a portion of a semiconductor CMOS imager wafer
in an interim stage of processing according to an
embodiment of the invention.
The Appellant discloses that insulating layer 315 is formed over substrate
310, and doped polysilicon layer 320 is formed over insulating layer 315.
Photogate insulator 342 is grown or deposited over layer 320 and is patterned over
polysilicon layer 320 above n-doped region 316. Spec. 17, 11. 10-11, 17-21.
Appellant's Figure 8, reproduced below, shows metal layer 326 deposited on
polysilicon layer 320 and photogate insulator 342. Spec. 18; 11. 1-2.
FIG. 8
Appellant's Fig. 8 depicts a partially cut away side view
of a portion of a semiconductor CMOS imager wafer
subsequent to Appellant's Fig. 7.
After metal layer 326 is deposited, the wafer is annealed to react with a
portion of polysilicon layer 320 to form conductive layer 325. Unreacted metal
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Appeal2013-008694
Application 12/619,296
layer 326 over insulating region 342 is then removed to arrive at the structure
illustrated in Appellant's Figure 9, reproduced below. Spec. 18, 11. 2-7.
FIG,. 9
Appellant's Fig. 9 depicts a partially cut away side view
of a portion of a semiconductor CMOS imager wafer
subsequent to Appellant's Fig. 8.
The Appellant discloses that a resist and mask (not shown) is then applied to
substrate 310 and the wafer is patterned and the silicide and polysilicon layers are
etched to form transfer gate 350 and reset gate 360 over substrate 310 as illustrated
in Appellant's Figure 10, reproduced below. Spec. 18, 11. 8-10.
FIG'. 10
Appellant's Figure 10 depicts a partially cut away side view
of a portion of a semiconductor CMOS imager wafer
subsequent to Appellant's Figure 9.
Gates 350 and 360 include doped polysilicon layer 320 covered by
conductive layer 325. Conductive layer 325 is selectively removed from substrate
310 as shown in Figure 10 by a wet or dry etch or other chemical and/or
mechanical methods in regions not protected by the patterned photoresist.
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Application 12/619,296
Conductive layer 325 remains over both transfer gate 350 and reset gate 360 after
the pattern mask is removed. Spec. 18, 11. 12-18.
Appellant's Figure 11, reproduced below, illustrates an essentially complete
photosensor cell. Spec. 19, 11. 14-15.
,
312 315
320
FIG4 11
I
lts
Appellant's Figure 11 depicts a partially cut away side view
of a portion of a semiconductor CMOS imager wafer
subsequent to Appellant's Figure 10.
Spacers 324 are formed along the sides of gate stacks 340, 350, and 360, and
a resist mask (not shown) is further used to shield areas of substrate 310 that are
not to be doped. Doped regions 312, 314, and 318 are then formed in substrate
310. Spec. 19, 11. 1-6.
The Appellant does not identify a floating diffusion node in this or any other
embodiment of the Appellant's invention. However, the Appellant does identify a
floating diffusion region 30 in Appellant's Figure 1 which is said to illustrate a
CMOS imager circuit of the related art. See Spec. 5, 1. 20 ("n+ region 30 is
typically called a floating diffusion region"). The Examiner finds that the floating
diffusion node recited in claim 87 corresponds to doped region 30 on the right side
of transfer gate 28 in Appellant's Figure 1 which, in tum, corresponds to doped
region 314 on the right side of transfer gate 3 50 in, for example, Figure 11. Ans.
1 1.
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Application 12/619,296
The Appellant does not disclose that the floating diffusion node is silicided
in the embodiment depicted in Appellant's Figure 1. Moreover, the Examiner
finds that "[i]n all instances disclosed in the instant disclosure, the silicides 325 on
the transistor gates, namely the transfer gate 350 and the reset gate 360, ... were
already carried out before the floating diffusion [region] 314 being [sic, is]
formed." Ans. 11 (emphasis added); see also Ans. 12 (the floating diffusion node
is not formed until after the silicide is formed and selectively removed). For this
reason, the Examiner finds there is no support or description for the limitation at
issue in claim 87.
The Appellant argues:
[I]n the semiconductor processing art, a region of a semiconductor
wafer is defined as a "floating diffusion node" based on its
corresponding location in a mask set. Such regions are referred to as
the "floating diffusion node" throughout the processing of the wafer
regardless of whether doping of that region has been carried out.
Therefore, a person of ordinary skill in the relevant art would readily
recognize that a "floating diffusion node upon which the silicide layer
is first formed and then substantially removed" does not only refer to
doped regions upon which the silicide layer is formed and then
substantially removed.
Reply Br. 12. 9
Significantly, the Appellant does not direct us to any evidence to support this
argument. Thus, we tum to the Appellant's Specification for guidance. See In re
Icon Health and Fitness, Inc., 496 F.3d 1374, 1379 (Fed. Cir. 2007) (During
examination, "claims [must be given] their broadest reasonable construction
consistent with the specification."). The Appellant discloses that doped region 314
is formed after the silicide layer or conductive layer 325 is removed. See Spec. 18,
9 Reply Brief dated June 26, 2013.
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Application 12/619,296
11. 14--16 (disclosing that conductive layer 325 is selectively removed from
substrate 310 as shown in Fig. 1 O); Spec. 19, 11. 5-8 (disclosing that "doped
regions 312, 314, 318 are then formed in the substrate 31 O" and are, for example,
n-type ). Thus, to the extent that the floating diffusion node recited in claim 87
corresponds to region 314 in Appellant's Figure 1, the floating diffusion node
would also be formed after removal of the silicide layer. See Spec. 5, 1. 20
(indicating that a floating diffusion region is a doped region). For this reason, the
Examiner's finding that the original disclosure does not describe the steps of
forming and then substantially removing a silicide layer from the floating diffusion
node is supported by a preponderance of the evidence.
As for the source follower transistor having a silicide gate coupled to the
floating diffusion node as recited in claims 90, 99, and 101, the Examiner finds that
the original disclosure "fail[ s] to mention anything regarding the gate material for
the source follower." Ans. 15.
Nonetheless, the Appellant argues that:
[A] person of ordinary skill in the relevant art would know from the
context of the specification to substitute structure/ram the CMOS
imager wafer portion of the Detailed Description into analogous
structure within the CMOS imager of the Related Art [i.e., admitted
prior art]. The ordinary practitioner would therefore understand that
because the CMOS imager of the Related Art includes a source
follower transistor 36 having a transistor gate ... , the speed of the
source follower transistor 36 would be improved by incorporating a
silicide or a barrier/metal layer into the transistor gate of the source
follower transistor 36.
App. Br. 16 (emphasis added; original emphasis deleted). For this reason, the
Appellant argues that one of ordinary skill in the art would have substituted the
selectively silicided transistor gate described in the Detailed Description for a
transistor gate within the source follower transistor of the related art. Reply Br. 14.
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To satisfy the written description requirement, an applicant must "convey
with reasonable clarity to those skilled in the art that, as of the filing date sought,
he or she was in possession of the invention." Vas-Cath, Inc. v. Mahurkar, 935
F.2d 1555, 1563-64 (Fed. Cir. 1991). "One shows that one is 'in possession' of
the invention by describing the invention, with all its claimed limitations, not that
which makes it obvious." Lockwood v. American Airlines, Inc., 107 F.3d 1565,
1572 (Fed. Cir. 1997). Thus, in this case, the Appellant's arguments relating to the
obviousness of incorporating a silicide into the gate of source follower transistor
36 in the related art (Appellant's Figure 1) do not show compliance with the
written description requirement of 35 U.S.C. § 112, first paragraph.
The rejection of claims 87-96 and 98-102 under 35 U.S.C. § 112, first
paragraph, is sustained.
2. Rejection (2)
As an initial matter, the Examiner concludes that the limitation "the floating
diffusion node upon which the silicide layer is first fonned and then substantially
removed" recited in claims 87 is a product-by-process limitation. Final 5 (citing In
re Thorpe, 777 F.2d 695, 697 (Fed. Cir. 1985) ("even though product-by-process
claims are limited by and defined by the process, determination of patentability is
based on the product itself')). Thus, the Examiner interprets the limitation "the
floating diffusion node upon which the silicide layer is formed and then
substantially removed" as the floating diffusion node is substantially free of
silicide. 10 Ans. 17; see also Final 6. The Examiner's interpretation is supported by
the record.
10 Similarly, the Examiner interprets "'the transistor source/drain atop which the
silicide layer is formed and substantially removed' [in product claims 103 and 104]
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The Examiner finds Merrill teaches that "the use of silicides should be
obviated where electrical leakage can result or when the coupling of photons is
inhibited, including over photo collection region, source region or drain region."
Final 22; see also Final 8. 11 Thus, the Examiner concludes that it would have been
obvious to one of ordinary skill in the art to use a floating diffusion node that is
substantially free of silicide in the CMOS imager of the admitted prior art. Final 8.
The Appellant does not direct us to any error in the Examiner's factual
findings. Rather, the Appellant argues:
Merrill describes a silicide exclusion mask which prevents
deposition of silicide on particular areas of a CMOS pixel array while
allowing silicide deposition on other areas of the array. . . . Merrill is
not concerned with silicide that is first formed and then substantially
removed and hence is not concerned with a floating diffusion node
upon which a silicide layer is first formed and then substantially
removed.
App. Br. 18 (original emphasis omitted).
The Appellant argues:
[B]ecause of differences in the processing steps that would [be]
carried out, a region "upon which the silicide is first formed and then
substantially removed" is structurally different than a region that is
masked to prevent silicide deposition. As an example, to remove the
silicide from the "floating diffusion node upon which the silicide is
first formed and then substantially removed", reactive ion etching may
be used which results in the underlying substrate being bombarded
with the etchant ions and affect such underlying substrate. Hence, the
claimed "floating diffusion node, being substantially free of silicide"
is not merely a process limitation but also defines a structure that is
... as the transistor source/drain is substantially free of silicide." Final 6; see also
Final 14.
11 The Examiner also finds that the absence of silicide from the floating diffusion
region corresponds to conventional structures in the admitted prior art and Fossum
where silicides are not provided on the floating diffusion region. Final 22.
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different than, for example, a region masked to prevent silicide
deposition as described by Merrill.
Reply Br. 16 (emphasis added; original emphasis omitted).
Suffice it to say that claim 87 does not recite that reactive ion etching is used
to remove the silicide from the floating diffusion node, and the Specification does
not disclose that selective removal of the silicide is limited to reactive ion etching.
See Spec. 18, 11. 14--16 (conductive layer 325 is selectively removed from substrate
310 "by a wet or dry etch or other chemical and/or mechanical methods"). Thus,
the Appellant has failed to show that the claimed CMOS imager is patentably
distinct from the CMOS imager described in the admitted prior art as modified by
Fossum, Park, and Merrill. In re Marosi, 710 F.2d 799, 803 (Fed. Cir. 1983)
("Where a product-by- process claim is rejected over a prior art product that
appears to be identical, although produced by a different process, the burden is
upon the applicants to come forward with evidence establishing an unobvious
difference between the claimed product and the prior art product.").
The rejection of claim 87 under 35 U.S.C. § 103(a) rejection is sustained.
3. Rejections (3}--{6)
The Appellant does not present any arguments in support of the separate
patentability of claims 88-96 and 98-111. App. Br. 19-21. Therefore, the
rejections of claims 88-96 and 98-111 under 35 U.S.C. § 103(a) are sustained.
C. DECISION
The decision of the Examiner is affirmed.
No time period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(l ).
AFFIRMED
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