Ex Parte RAWSON et alDownload PDFPatent Trial and Appeal BoardMay 13, 201612789062 (P.T.A.B. May. 13, 2016) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 121789,062 05/27/2010 75916 7590 05/17/2016 IBM AUS IPLA W (GLF) c/o Garg Law Firm, PLLC 4521 Copper Mountain Lane Richardson, TX 75082 FIRST NAMED INVENTOR FREEMAN LEIGH RAWSON III UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. A US920100220US 1 7897 EXAMINER ONAT,UMUT ART UNIT PAPER NUMBER 2194 NOTIFICATION DATE DELIVERY MODE 05/1712016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): dpandya@garglaw.com uspto@garglaw.com garglaw@gmail.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte FREEMAN LEIGH RAWSON III, WILLIAM EV AN SPEIGHT, and LIXIN ZHANG Appeal2014-002164 Application 12/789,062 Technology Center 2100 Before JASON V. MORGAN, MELISSA A. HAAPALA, and NABEEL U. KHAN, Administrative Patent Judges. KHAN, Administrative Patent Judge. DECISION ON APPEAL Appellants 1 appeal under 35 U.S.C. § 134(a) from the final rejections of claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. 1 According to the Appeal Brief, the real party in interest is International Business Machines Corporation. App. Br. 2. Appeal2014-002164 Application 12/789,062 THE INVENTION The invention relates to an "improved register allocation in a simultaneous multithreaded processor." Abstract. Independent claim 1 is illustrative of the subject matter argued by Appellants (see infra, "Analysis" section) and reproduced below with emphasis on an at-issue limitation (italicization and paragraphing added). 1. A computer implemented method for register allocation in a multi-threading data processing environment, the computer implemented method comprising: determining that a thread of an application in the data processing environment needs a higher number of physical registers than a second number of physical registers in a set of physical registers that is available to allocate to the thread; configuring the thread to utilize a logical register that is mapped to a memory register, wherein a physical register is a hardware register, the memory register comprises memory space configured to operate as an additional physical register outside the set of physical registers, wherein the logical register is a data structure that the thread references in a manner the thread references a physical register in the set of physical registers, and wherein the thread performs an operation on the logical register to cause the operation on one of the physical register and the memory register; and executing the thread. Independent claims 14 and 20 also recite limitations substantially similar to the at-issue limitation. Each of the remaining claims depends from one of independent claims 1, 14, and 20. 2 Appeal2014-002164 Application 12/789,062 EXAivITI'IJER'S REJECTIONS Claims 1, 2, 4-12, 14-17, and 20 are rejected under 35 U.S.C. § 102(e) as being anticipated by Abdallah (US 2010/0161948 Al; June 24, 2010). Final Act. (Jan. 23, 2013) 5-13. Claims 3 and 13 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Abdallah and Wilson (US 2007 /0094483 A 1; April 26, 2007). Final Act. 14-16. Claims 18 and 19 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Abdallah and Sperber (US 2009/0327661 Al; Dec. 31, 2009). Final Act. 16-18. ANALYSIS The Examiner rejects all claims over Abdallah alone or in view of other references. Appellants contend the Examiner has not established that, as found for all rejections, Abdallah's tag array, data array, register cache, and outgoing thread respectively constitute a logical register, memory register, physical registers, and thread as recited by the at-issue limitation. App. Br. 15-16; see Ans. 7-9 (citing Abdallah ,-i 34); Final Act. 5-6 (citing Abdallah ,-i,-i 34, 61-63).2 Appellants argue, in pertinent part: Examiner has analogized the logical register with Abdallah' stag. Abdallah's tag does not operate in the manner of claimed logical register. As described above, Abdallah's tag is a location in the memory cache where the register information of an outgoing thread can be stored while the incoming thread re-uses the 2 Abdallah' s tag array and data array are each part of the memory cache. Abdallah ,-i 62. The Examiner reads the at-issue limitation's logical register and memory register respectively on Abdallah' s tag and memory cache; but plainly and more particularly means Abdallah's tag array and data array. 3 Appeal2014-002164 Application 12/789,062 register batch. Nothing in the entire 01sc10sure of Abdallah teaches that the outgoing thread can use the tag to reference memory cache in the manner of referencing a register in Abdallah's register batch. In fact, Abdallah teaches nothing other than a viable eviction location in memory as a possible use for the tag, much less allow the outgoing thread to reference (the tag)[.] Examiner misinterprets Abdallah' s "tag." Examiner alleges that Abdallah teaches claim l's feature, "wherein the thread performs an operation on the logical register to cause the operation on one of the physical register" because Abdallah teaches, "(see e.g. paragraph 34: [']tags to the register locations such that they are accessed by the tags that include the actual register number')." In fact, Abdallah teaches that the tag is used to access the register, not that the tag is operable in the manner of a logical register or that a tag allows accessing a logical register to manipulate the register. In other words, a thread accesses the register using tag information. Nothing in this teaching teaches that the thread performs an operation on a tag. App. Br. 15 (original emphasis; italics omitted). 3 We agree with the above argument, insofar as the portions of Abdallah relied upon by the Examiner to disclose the "logical register" (tag array), particularly paragraphs 34 and 61-63, do not state whether it is the outgoing thread that operates on the tag array; much less operates on the tag array to thereby cause performance of the same operation on the memory cache. Rather, as to use of the tag array, Abdallah's cited disclosure states: "[T]he tag array is accessed upon any load or store instruction that is a part of a context switch, which is also known as saving and restoring the context." 3 Appellants present additional arguments in the Appeal Brief. However, because the identified issue is dispositive of the appeal, we do not address these additional arguments. 4 Appeal2014-002164 Application 12/789,062 Abdallah iJ 62. The Examiner does not establish the cited sections of Abdallah disclose the outgoing thread uses the above load/store instruction to operate on the tag array (logical register) in a manner the thread references a physical register, or that an operation performed on the tag array causes performance of the same load/store operation on the memory cache (memory register) and/or physical register. We therefore agree with Appellants that the Examiner has not established Abdallah discloses the at-issue limitation. The Examiner does not rely on the additional references of record to teach or suggest this limitation. Accordingly, we do not sustain the: anticipation rejection of claims 1, 2, 4-12, 14-17, and 20 over Abdallah; obviousness rejection of claims 3 and 13 over Abdallah and Wilson; and obviousness rejection of claims 18 and 19 over Abdallah and Sperber. DECISION The Examiner's rejections of claims 1-20 are reversed. REVERSED 5 Copy with citationCopy as parenthetical citation