Ex Parte Rammel

Patent Trial and Appeal Board

Sep 26, 2013

10720614 (P.T.A.B. Sep. 26, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte MARTIN G. RAMMEL
____________________

Appeal 2011-001680
Application 10/720,614
Technology Center 2100
____________________

Before JEAN R. HOMERE, MARC S. HOFF, and HUNG H. BUI,
Administrative Patent Judges.

BUI, Administrative Patent Judge.

DECISION ON APPEAL
Appellant
1
seeks our review under 35 U.S.C. § 134(a) of the
Examiner’s final rejection of claims 31-37.
2
We have jurisdiction under 35
U.S.C. § 6(b).
We AFFIRM-IN-PART.
3

1
Real Party in Interest is The Boeing Company.
2
Claims 1-16 and 18-30 are cancelled. Claim 17 is pending, but is not on
appeal.
3
Our decision refers to Appellant’s Appeal Brief filed April 22, 2010
(“App. Br.”); Examiner’s Answer mailed July 20, 2010 (“Ans.”); Final
(Footnote continued on next page.)
Appeal 2011-001680
Application 10/720,614

2

STATEMENT OF THE CASE
Appellant’s Invention
Appellant’s invention relates to methods and apparatus for improving
the speed of computational simulations using cost-effective, hardware-based
solutions. See Spec., p. 4, ll. 5-9. According to Appellant, the speed is
improved by offloading a portion of the simulation from a host computer to
a field programmable gate array (FPGA), and then managing the dataflow
between the computer and the FPGA. Thus, instead of the computer running
the entire simulation, a first portion is performed by the computer, and a
second portion is performed by the FPGA. See App. Br. 2.
Claims on Appeal
Claims 31 and 25 are the independent claims on appeal. Claim 31 is
illustrative of Appellant’s invention, and is reproduced below with disputed
limitations emphasized:
31. A method of performing a numerical simulation
with a Field Programmable Gate Array (FPGA) and a separate
central processing unit (CPU), the method comprising:
using the CPU to perform a numerical simulation
including generating input signals and sending the input signals
to the FPGA;
using the FPGA to apply a model to the input signals and
send results of the model back to the CPU, the FPGA also
generating a first output that marks data as valid or invalid, a
second output that indicates the first sample of each frame, and
a third output that indicates when the model can accept data;
and

Office Action mailed January 13, 2010 (“FOA”); and the original
Specification filed November 24, 2003 (“Spec.”).
Appeal 2011-001680
Application 10/720,614

3

wherein the CPU uses the results in the numerical
simulation and the outputs to maintain data flow with the
FPGA.

Evidence Considered
Ozawa U.S. 2002/0103839 A1 Aug. 1, 2002
Ballagh U.S. 6,883,147 B1 Apr. 19, 2005
Answers.com Dictionary Definition of “Floating-point”
Admitted Prior Art (APA) Specification, pages 1-2.

Examiner’s Rejections
(1) Claim 31 stands rejected under 35 U.S.C. § 102(e) as being
anticipated by Ballagh. Ans. 3-5.
(2) Claims 32-37 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Ballagh and Appellant’s Admitted Prior Art (APA). Ans.
5-8.

Issues on Appeal
Based on Appellant’s arguments, the dispositive issues on appeal are:
(1) Whether the Examiner erred in rejecting claim 31 under 35
U.S.C. § 102(e) as being anticipated by Ballagh. In particular, the issue
turns on whether Ballagh discloses “a numerical simulation” and related
limitations of Appellant’s claim 31. Ans. 9-21.
(2) Whether the Examiner erred in rejecting claims 32-37 under 35
U.S.C. § 103(a) as being unpatentable over Ballagh and Appellant’s
Admitted Prior Art (APA). The issue turns on whether the combination of
Ballagh and APA discloses or renders obvious limitations of claims 32-37.
Ans. 21-22.
Appeal 2011-001680
Application 10/720,614

4

ANALYSIS
§ 102(e) Rejection of Claim 31 by Ballagh
Appellant contends that the Examiner erred in rejecting claim 31
under 35 U.S.C. § 102(e) as being anticipated by Ballagh. App. Br. 6-10. In
particular, Appellant argues that the Examiner’s interpretation of the claim
term “numerical simulation” to encompass “a fixed or floating point
operation” is incorrect, unreasonable, and inconsistent with Appellant’s
Specification. Id. at 8. According to Appellant,
numerical simulations are used to model different types of
physical phenomena. In the field of aerospace engineering,
numerical simulations can be used to predict electromagnetic
scattering from reflective bodies. The detailed description
provides a specific example: a radar simulation.

Id. (emphasis added).

In contrast to a “numerical simulation,” Appellant argues that “a fixed
or floating point operation is but one operation in a numerical simulation.”
Id. (emphasis added).
We do not find Appellant’s arguments persuasive to demonstrate
reversible error in the Examiner’s position. See In re Jung, 637 F.3d 1356,
1365 (Fed. Cir. 2011). At the outset, we note that claim terms are given
their broadest reasonable interpretation consistent with the specification. In
re Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1369, (Fed. Cir. 2004).
However, in interpreting claims care must be exercised as there is an
important distinction between interpreting claims in light of the specification
and reading limitations into the claims from the specification. Comark
Commc'ns, Inc. v. Harris Corp., 156 F.3d 1182, 1186 (Fed. Cir. 1998).
Appeal 2011-001680
Application 10/720,614

5

While claims are interpreted in light of the specification, limitations from the
specification must not be read into the claims. In re Van Geuns, 988
F.2d 1181, 1184 (Fed. Cir. 1993).
In the context of Appellant’s Specification, applications of “a
numerical simulation” are described, including radar, medical research,
aerospace engineering, electrical engineering, geology, atmospheric science,
and many other scientific endeavors. See Appellant’s Spec., page 1, ll. 19-
26. However, there is no explicit definition of such a numerical simulation.
In the absence of such an explicit definition, the Examiner may adopt the
broadest reasonable definition of the term consistent with Appellant’s
Specification. See In re Morris, 127 F.3d 1048, 1053-54 (Fed. Cir. 1997).
In the instant appeal, the Examiner has adopted Ballagh’s teaching of
“simulating system parameters such as sample rates, data precision” and
“arithmetic values using floating point or fixed point” as Appellant’s
claimed “numerical simulation,” i.e., that the “numerical simulation”
encompasses the “simulating system parameters such as sample rates, data
precision” and “arithmetic values using floating point or fixed point.” Ans.
9-13 (citing Ballagh, col. 1, ll. 32-46; col. 4, ll. 11-13 and 20-23). As
correctly found by the Examiner, the modeling and simulation of these
system parameters/arithmetic values represented by floating point or fixed
point are described by Ballagh to create a circuit design and predict a design
system performance. Ans. 12.
In view of such explanations, we find the Examiner’s broad
interpretation of the claim term “numerical simulation” reasonable in view
of Appellant’s Specification, especially when such “floating-point
Appeal 2011-001680
Application 10/720,614

6

operations” are also known in the art as an example of a simulation program.
Ans. 13 (citing Sagawa, U.S. Patent No. 5,963,731, col. 34, ll. 16-24).
Appellant further argues that “Ballagh provides no guidance
whatsoever for speeding up a numerical simulation,” and “does not describe
a single feature” of Appellant’s claim 31. App. Br. 9. According to
Appellant, (1) Ballagh is silent about a portion of a simulation being
offloaded from a processor to an FPGA, whereby the processor runs a first
portion of the simulation and the FPGA runs a second portion of the
simulation; (2) Ballagh only describes a simulation for designing an FPGA,
wherein the entire simulation is run on a single computer; and (3) Ballagh is
silent about data flow between the external processor and the FPGA. Id.
We are cognizant of the differences between Appellant’s disclosure
and Ballagh’s disclosure. As correctly found by the Examiner, Ballagh
discloses data flow between the external processor and the FPGA. Ans. 4-5,
15 (citing Ballagh, col. 5, ll. 29-38, and FIG. 2). However, as recognized by
the Examiner, neither the speed up of a numerical simulation nor the
offloading of a portion of a simulation between the processor and the FPGA
is recited in Appellant’s claim 31. Ans. 14-15. As such, Appellant’s
arguments are not commensurate in scope with the limitations of claim 31.
See In re Self, 671 F.2d 1344, 1348 (CCPA 1982). Unclaimed features
cannot impart patentability to claims. In re Hiniker Co., 150 F.3d 1362,
1369 (Fed. Cir. 1998). We therefore decline to read the argued limitations
into the claims.
We also note that the Examiner has made extensive factual findings
regarding Ballagh with respect to each limitation of Appellant’s claim 31,
including the data flow between the external processor and the FPGA. Ans.
Appeal 2011-001680
Application 10/720,614

7

3-4 and 9-21. Appellant does not contest the Examiner’s factual findings
regarding Ballagh, as evidenced from the absence of a Reply Brief. Nor
does Appellant explain why Examiner’s factual findings are in error.
For the reasons set forth above, Appellant has not persuaded us of
error in the Examiner’s rejection of claim 31. Accordingly, we sustain the
Examiner’s anticipated rejection of claim 31 based on Ballagh.

§ 103(a) Rejection of Claims 32-37 over Ballagh and APA
With respect to dependent claims 32-33, Appellant repeats the same
arguments presented against the § 102(e) rejection of claim 31, i.e., “Ballagh
does not teach or suggest offloading a specific element of a numerical
simulation – the FFT – from a host computer to an FPGA.” App. Br. 11. In
addition, Appellant also argues that the Examiner fails to provide: (1)
articulated reasoning about offloading a specific element – the FFT – from a
host computer to an FPGA and (2) rationale to support a conclusion of
obviousness. App. Br. 11-12.
We are not persuaded. As previously discussed, these alleged features
of patentability are not recited in Appellant’s claim 31. Moreover, we find
the Examiner’s factual findings regarding Ballagh and Appellant’s Admitted
Prior Art (APA) are supported by a preponderance of evidence, and, as such,
agree with the Examiner’s conclusion that:

It would have been obvious to a person having ordinary
skill in the art at the time the invention was made to combine
APA's teaching into Ballagh's teaching. One would have been
motivated to do so to transform a digitized waveform in the
time domain into a digital representation in the frequency
domain by using Simulink simulation software product as
Appeal 2011-001680
Application 10/720,614

8

suggested by APA (e.g., page 2: 5-9 and 20-23), and not just
with a mere ‘conclusory statement’ as Appellant asserted.

Ans. 21.
With respect to dependent claim 34, Appellant presents no arguments
regarding patentability of this claim separately from independent claim 31.
As such, claim 34 fall together with independent claim 31. See 37 C.F.R.
§ 1.37(c)(1)(vii) (stating that “the failure of Appellant to separately argue
claims which Appellant has grouped together shall constitute a waiver of any
argument that the Board must consider the patentability of any grouped
claim separately”).
For the reasons set forth above, Appellant has not persuaded us of
error in the Examiner’s rejection of claims 32-34. Accordingly, we sustain
the Examiner’s obviousness rejection of claims 32-34.
With respect to independent claim 35, Appellant repeats the same
arguments presented against the § 102(e) rejection of claim 31, i.e., “Ballagh
does not teach or suggest offloading a specific element of a numerical
simulation – the FFT – from a host computer to an FPGA.” App. Br. 11. In
addition, Appellant also argues that the Examiner fails to provide: (1)
articulated reasoning about offloading a specific element – the FFT – from a
host computer to an FPGA and (2) rationale to support a conclusion of
obviousness. App. Br. 11-12.
In response thereto, the Examiner finds that the offloading of different
portions of a numerical simulation is disclosed by Ballagh. Ans. 21.
However, we disagree with the Examiner’s finding regarding
independent claim 35. In contrast with independent claim 31, Appellant’s
claim 35 expressly recites and requires both a central processing unit (CPU)
Appeal 2011-001680
Application 10/720,614

9

and a field programmable gate array (FPGA) perform “different portions of
a numerical simulation.” Neither Ballagh nor Appellant’s Admitted Prior
Art, whether taken individually or in combination, discloses or suggests that
both the central processing unit (CPU) and the field programmable gate
array (FPGA) perform “different portions of a numerical simulation,” i.e.,
running a first portion of a simulation in a CPU and running a second
portion of the simulation in the FPGA, as argued by Appellant. App. Br. 11.
For the reasons set forth above, Appellant has persuaded us of error in
the Examiner’s rejection of independent claim 35. Accordingly, we will not
sustain the Examiner’s obviousness rejection of claim 35 and its dependent
claims 36-37.

CONCLUSION
On the record before us, we conclude that the Examiner has not erred
in rejecting: (1) claim 31 under 35 U.S.C. § 102(e) as being anticipated by
Ballagh; and (2) claims 32-34 under 35 U.S.C. § 103(a) as being
unpatentable over Ballagh and Appellant’s Admitted Prior Art (APA).
However, we conclude that the Examiner has erred in rejecting claim 35 and
its dependent claims 36-37 under 35 U.S.C. § 103(a) as being unpatentable
over Ballagh and Appellant’s Admitted Prior Art (APA).

DECISION
As such, we AFFIRM the Examiner’s final rejection of claims 31-34;
however, we REVERSE the Examiner’s final rejection of claims 35-37.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
Appeal 2011-001680
Application 10/720,614

10

AFFIRMED-IN-PART

ELD