Ex Parte Ramaraju

Patent Trial and Appeal Board

Sep 26, 2016

13213831 (P.T.A.B. Sep. 26, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/213,831 08/19/2011 Ravindraraj Ramaraju
53364 7590 09/28/2016
NXP-TERRILE, CANNATTI, CHAMBERS & HOLLAND - FSL
6501 William Cannon Drive West
AUSTIN, TX 78735
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
NM46074HC 9005
EXAMINER
CY GIEL, GARY W
ART UNIT PAPER NUMBER
2137
NOTIFICATION DATE DELIVERY MODE
09/28/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ip.department.us@nxp.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte RA VINDRARAJ RAMARAJU
Appeal2015-001650
Application 13/213,831
Technology Center 2100
Before JAMES R. HUGHES, LINZY T. McCARTNEY, and
MATTHEW J. McNEILL, Administrative Patent Judges.
McNEILL, Administrative Patent Judge.
DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner's
rejection of claims 1--4, 9-13, and 15-20.2 We have jurisdiction under
35 U.S.C. § 6(b).
We reverse.
1 According to Appellant, the real party in interest is Freescale
Semiconductor, Inc. App. Br. 1.
2 Claims 5-8 and 14 have been objected to as being dependent upon a
rejected base claim, but the Examiner indicates these claims would be
allowable if rewritten in independent form including all of the limitations of
the base claim and any intervening claims. Final Act. 18.
Appeal2015-001650
Application 13/213,831
STATEMENT OF THE CASE
Introduction
Appellant's application relates to placing a memory unit in parallel
with an operand adder circuit to enable generation of speculative way
hit/miss information directly from the operands without using the output
sum of the operand adder. Abstract. Claim 1 is illustrative of the subject
matter on appeal and reads as follows with the disputed limitations
italicized:
1. A method for generating a speculative miss signal from
base and offset operands without requiring addition of the base
and offset operands comprising:
receiving a base operand and offset operand, wherein each
operand comprises a first plurality of address bits comprising tag
bits and index bits;
pairing each address bit from the base operand with a
corresponding address bit from the offset operand, thereby
forming a plurality of index bit pairs and a plurality of tag bit
pairs;
applying the plurality of index bit pairs and the plurality
of tag bit pairs to an indexed content-addressable memory
(CAM) array to generate two speculative miss signals from two
speculatively indexed rows by using a two stage dynamic
comparator to generate a speculative odd miss signal and a
speculative even miss signal, respectively, in response to a
delayed evaluate signal that is delayed with respect to a control
word line signal applied to the two speculatively indexed rows;
and
selecting one of the speculative odd miss signal and
speculative even miss signal for output based on a sum value
computed by adding at least the least significant index bit of the
base operand with the least significant index bit of the offset
operand.
2
Appeal2015-001650
Application 13/213,831
The Examiner's Rejections
Claims 1, 10-12, and 16-18 stand provisionally rejected on the
ground of non-statutory double patenting over claims 1-5, 12, 13, 15, 16,
and 18-20 of co-pending Application No. 13/213,900 ("the '900
Application"). Ans. 2.
Claim 9 stands provisionally rejected on the ground of obviousness-
type non-statutory double patenting over claims 1 and 11 of the '900
Application and Ramaraju et al. (US 2007 /0094480 Al; Apr. 26, 2007)
("Ramaraju 2007"). Ans. 2.
Claims 1--4, 9-13, and 15-20 stand rejected under 35 U.S.C. § 103(a)
as unpatentable over Ramaraju 2007 and Ramaraju et al. (US 2010/0306302
Al; Dec. 2, 2010) ("Ramaraju 2010"). Ans. 2.
ANALYSIS
Double Patenting
Appellant argues the Examiner's double patenting rejecting of claims
1, 10-12, and 16-18 is in error because the '900 Application does not
disclose a "delayed evaluate signal." App. Br. 5-6. The Examiner finds the
'900 Application claims disclose a delayed evaluate signal because "any
evaluate signal used to evaluate the content of a memory is necessarily
delayed 'with respect to a control word line signal applied to the two
speculatively indexed rows' because a control wordline signal is used to
access a memory space." Ans. 3. The Examiner notes that the present
claims do "not describe the degree of delay or the mechanism of delay." Id.
3
Appeal2015-001650
Application 13/213,831
We disagree with the Examiner's interpretation of "delayed evaluate
signal," which is overly broad and effectively reads the "delayed" limitation
out of the claim. The broadest reasonable interpretation of "a delayed
evaluate signal that is delayed with respect to a control word line signal
applied to the two speculatively indexed rows" requires more than an
evaluate signal used to evaluate the content of a memory accessed by a
control wordline signal. Ans. 3. For example, the Specification teaches
delay logic circuitry 1085 that is used to impose a delay on the evaluate
signal. Spec. Spec. ,-i 50, Fig. 10 (elements 1051, 1085). Contrary to the
Examiner's finding, the imposed delay is in addition to the time it takes for
the evaluate signal to access the memory. See id. Accordingly, on the
record before us, Appellant has persuaded us that the Examiner has not
established that the '900 Application claims teach a "delayed evaluate
signal" as that term is used in claims 1, 10, and 17. We, therefore, do not
sustain the double patenting rejection of claims 1, 10, and 17.
Obviousness
Appellant argues the Examiner erred in finding the combination of
Ramaraju 2007 and Ramaraju 2010 teaches or suggests generating and
selecting speculative miss signals from an "indexed CAM array," as recited
in claim 1. App. Br. 8-13; Reply Br. 5-9. In particular, Appellant argues
the Examiner concedes Ramaraju 2007 teaches memory access for
conventional random access memory (RAM) instead of an indexed CAM
array, while Ramaraju 2010 teaches memory access for conventional
content-addressable memory instead of an indexed CAM array. App. Br. 9.
4
Appeal2015-001650
Application 13/213,831
The Examiner responds that "the term 'indexed' does not imply any
additional structure other than that which is recited in the claims." Ans. 5.
The Examiner asserts that "addressing is a mechanism for indexing" and,
therefore, the broadest reasonable interpretation of an "indexed CAM array"
includes the structure of the combined system of Ramaraju 2007 and
Ramaraju 2010. Ans. 5-6.
The Examiner's interpretation of the term "indexed content-
addressable memory (CAM) array" is overly broad because not all
addressable memory is "indexed" as the Examiner suggests. The
Specification teaches the preferred embodiment uses content addressable
memory that is addressed using "tag" bits 0--4 7 and "index" bits 48-51.
Spec. ,-i 20. This "indexed" content addressable memory is different from
conventional content addressable memory, which compares operand bits to
the content of each memory location without any separate index bits. See,
e.g., Ramaraju 2010 ,-i 17 (teaching content addressable memory that
compares operand bits to "all of the bit locations" to identify hits and
misses). Moreover, because "addressable" and "indexed" are separate
limitations in the claim, the Examiner's interpretation effectively reads the
"indexed" limitation out of the claim by rendering it superfluous to
"addressable."
Appellant has persuaded us that an "indexed CAM array," as recited
in the claims, compares the data on the wordline signal only to the indexed
CAM entries, while a conventional CAM array compares the data on the
wordline signal to every entry in the CAM. Accordingly, on the record
before us, we are persuaded by Appellant's arguments that the Examiner has
not identified sufficient evidence or provided sufficient explanation as to
5
Appeal2015-001650
Application 13/213,831
how the combination of Ramaraju 2007 and Ramaraju 2010 teaches or
suggests an "indexed content-addressable memory (CAM) array," as recited
in independent claims 1, 10, and 17.
CONCLUSIONS
On the record before us and in view of the analysis above, Appellant
has persuaded us that the Examiner erred in issuing the non-statutory double
patenting rejection of claims 1, 10, and 1 7. Therefore, we do not sustain the
non-statutory double patenting rejection of claims 1, 10, and 17. We also do
not sustain the non-statutory double patenting rejections of claims 11, 12,
16, and 18, which depend therefrom.
Claim 9, which depends from claim 1, stands rejected under non-
statutory obviousness-type double patenting over the '900 Application and
Ramaraju 2007. The Examiner has not found, nor do we find, that Ramaraju
2007 remedies the identified deficiency in the '900 ,,L\ .. pplication.
Accordingly, we also do not sustain the non-statutory obviousness-type
double patenting rejection of claim 9.
On the record before us and in view of the analysis above, Appellant
has persuaded us that the Examiner erred in rejecting claim 1 as obvious
over Ramaraju 2007 and Ramaraju 2010. Therefore, we do not sustain the
rejection of claim 1, independent claims 10 and 17 which recite similar
limitations, and claims 2--4, 9, 11-13, 15, 16, and 18-20 dependent
therefrom.
6
Appeal2015-001650
Application 13/213,831
DECISION
We reverse the decision of the Examiner to reject claims 1--4, 9-13,
and 15-20.
REVERSED
7