Ex Parte Rajwade et al

Patent Trials and Appeals Board

May 1, 2019

14922611 - (D) (P.T.A.B. May. 1, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/922,611 10/26/2015
88032 7590 05/03/2019
Jordan IP Law, LLC
12501 Prosperity Drive, Suite 401
Silver Spring, MD 20904
FIRST NAMED INVENTOR
Shantanu R. Rajwade
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
P87243 7652
EXAMINER
TRAN,UYENB
ART UNIT PAPER NUMBER
2824
NOTIFICATION DATE DELIVERY MODE
05/03/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
info@jordaniplaw.com
admin@jordaniplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SHANTANU R. RAJWADE, AKIRA GODA,
PRANAV KALAVADE, KRISHNA K. PARAT, andHIROYUKI SANDA
Appeal 2018-005815
Application 14/922,611
Technology Center 2800
Before CATHERINE Q. TIMM, BRIAND. RANGE, and
DEBRA L. DENNETT, Administrative Patent Judges.
TIMM, Administrative Patent Judge.
DECISION ON APPEAL 1
STATEMENT OF THE CASE
1 In explaining our Decision, we cite to the Specification of October 31,
2016 (Spec.), Final Office Action of February 10, 2017 (Final), Appeal Brief
of October 9, 2017, Response to Notice of Non-Compliant Appeal Brief of
November 6, 2017 (Resp. to Notice of Non-Compliant Appeal Br.),
Examiner's Answer of March 26, 2018 (Ans.), and Reply Brief of May 18,
2018 (Reply Br.).
Appeal 2018-005815
Application 14/922,611
Pursuant to 35 U.S.C. § 134(a), Appellant2 appeals from the
Examiner's decision to reject claims 1, 4-8, 11-15, and 18-22 under 35
U.S.C. § 103 as obvious over Costa '2573 and claims 2, 3, 9, 10, 16, 17, and
23-25 as obvious over Costa '257 in view of Costa '431.4 We have
jurisdiction under 35 U.S.C. § 6(b ).
We REVERSE.
The claims are directed to an apparatus (see, e.g., claims 1 and 12), a
system (see, e.g., claim 12), and a method (see, e.g., claim 19) relating to a
memory structure including an array ofNAND strings that can be erased in
sub-blocks. Spec. ,-J,-J 11, 13. Claim 1, with the limitations at issue in this
appeal highlighted, is illustrative:
1. An apparatus comprising:
a sub-block segmenter to identify a target sub-block of
memory to be partially or wholly erased;
a drain-side leakage driver to trigger a leakage current
condition in one or more target select gate drain-side (SGD)
devices associated with the target sub-block, wherein the drain-
side leakage driver is to set, via a plurality of gate pulses, a gate
voltage of the one or more target SGD devices to a value that
generates a reverse bias voltage that exceeds a threshold
corresponding to the leakage current condition;
a drain-side leakage inhibitor to inhibit the leakage
current condition in one or more remaining SGD devices
associated with remaining sub-blocks of memory, wherein the
drain-side leakage inhibitor is to set a gate voltage of the one or
2 Intel Corporation is the applicant under 37 C.F.R. § 1.46 and is identified
as the real party in interest. Appeal Br. 3.
3 Costa et al., US 2013/0279257 Al, published October 24, 2013.
4 Costa et al., US 8,913,431 Bl, issued December 16, 2014.
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Appeal 2018-005815
Application 14/922,611
more remaining SGD devices to a value that does not generate a
reverse bias voltage that exceeds the threshold; and
a source-side leakage inhibitor to inhibit the leakage
current condition in one or more select gate source-side (SGS)
devices associated with the target sub-block.,
wherein the target sub-block includes a common SGD
select line to connect a gate of a first SGD device of a first
NAND string of the target sub-block to a gate of a second SGD
device of a second NAND string of the target sub-block, and
wherein the first NAND string is connected to a first
source line and the second NAND string is connected to a
second source line.
Resp. to Notice of Non-Compliant Appeal Br. 2 ( claims appendix).
OPINION
All of the claims require two source lines connected to two different
NAND strings as recited in claim 1. See, e.g., claims 1, 5, 12, and 19.
Appellant has identified a reversible error in the Examiner's finding
that Costa '257 teaches the two source lines required by Appellant's claims.
Appeal Br. 12-16; Reply Br. 8. The Examiner finds that Costa '257
discloses connecting the source end (Fig. 3A: SSE2) of the first NAND
string (Fig. 3C: NAND string NS4) to a first line (Examiner's mark-up of
Fig. 3A: first line), and connecting the source end (Fig. 3A: SSEO) of the
second NAND string (Fig. 3C: NAND string NSO) to a second line (Fig.
3A: SLO). Final 5-6; see also Final 7 (annotated Fig. 3A of Costa '257);
Ans. 4 (annotated Fig. 3A). In other words, the first source line, according
to the Examiner, is the line running vertically from the second source line
SLO to SSE2 at the location of the arrow in annotated Figure 3A. Final 7.
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Appeal 2018-005815
Application 14/922,611
We agree with Appellant that the arrow points to source line SLO of Costa
'257 and is, thus, not a separate source line from source line SLO. Appeal
Br. 15. In fact, as pointed out by Appellant, Costa '257 expressly teaches
"[a] source line SLO connects SSEO and SSE2." Costa '257,-J 79. Costa
'257 does not identify the vertical portion of the line as a separate source
line such that "the first NAND string is connected to a first source line and
the second NAND string is connected to a second source line" as required by
the claims.
The Examiner's reliance on Costa' 4 31 to reject dependent claims does
not cure the deficiency.
CONCLUSION
We do not sustain the Examiner's rejections.
DECISION
The Examiner's decision is reversed.
REVERSED
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